Multi-level bridge interconnects

A semiconductor device comprising:

• a first chip layer comprising a first semiconductor chip having a plurality of interconnects;
• a second chip layer comprising a second semiconductor chip having a plurality of interconnects;
• a third chip layer comprising a third semiconductor chip having a plurality of interconnects, wherein the first semiconductor chip is stacked on the second semiconductor chip, wherein the second chip layer is stacked on the third chip layer, and wherein the first chip layer, the second chip layer, and the third chip layer are arranged such that a back side of the first semiconductor chip faces a front side of the second semiconductor chip, and a back side of the second semiconductor chip faces a front side of the third semiconductor chip;
• wherein at least one interconnect of the second semiconductor chip comprises a first through silicon via electrically coupling the back side of the second semiconductor chip to the front side of the second semiconductor chip, and wherein the first through silicon via extends to the back side of the second semiconductor chip to be coplanar with a back side surface of the second semiconductor chip and is not coplanar with a front side surface of the second semiconductor chip;
• and
• wherein at least one interconnect of the first semiconductor chip comprises a second through silicon via electrically coupling the back side of the first semiconductor chip to the front side of the first semiconductor chip, and wherein the second through silicon via extends to the back side of the first semiconductor chip to be coplanar with a back side surface of the first semiconductor chip and is not coplanar with a front side surface of the first semiconductor chip.

A method of manufacturing a semiconductor device, comprising:

• mounting a first semiconductor chip, a second semiconductor chip, and a first interconnect chip together to form a first chip layer, wherein the first semiconductor chip, the second semiconductor chip, and the first interconnect chip each have a plurality of interconnects with at least one interconnect comprising a thru silicon via electrically coupling a substrate portion of a respective semiconductor chip to an interconnect portion of the respective semiconductor chip;
• bonding a third semiconductor chip and a fourth semiconductor chip to the first chip layer to form a second chip layer, wherein the third semiconductor chip and the fourth semiconductor chip each have a plurality of interconnects with at least one interconnect comprising a thru silicon via electrically coupling a substrate portion of a respective semiconductor chip to an interconnect portion of the respective semiconductor chip, wherein a first interconnect of the first semiconductor chip is coupled to a first interconnect of the third semiconductor chip, and a first interconnect of the first interconnect chip is electrically coupled to a second interconnect of the third semiconductor chip, and wherein a second interconnect of the first interconnect chip is electrically coupled to a first interconnect of the fourth semiconductor chip, and a first interconnect of the second semiconductor chip is electrically coupled to a second interconnect of the fourth semiconductor chip;
• and
• bonding a fifth semiconductor chip, a sixth semiconductor chip, and a second interconnect chip to the second chip layer to form a third chip layer, wherein the fifth semiconductor chip, the sixth semiconductor chip, and the second interconnect chip each have a plurality of interconnects, wherein a third interconnect of the second semiconductor chip is coupled to a first interconnect of the fifth semiconductor chip, and a fourth interconnect of the second semiconductor chip is electrically coupled to a first interconnect of the second interconnect chip, and wherein a third interconnect of the fourth semiconductor chip is electrically coupled to a second interconnect of the second interconnect chip, and a fourth interconnect of the fourth semiconductor chip is electrically coupled to a first interconnect of the sixth semiconductor chip.