Bottom dielectric isolation integration with buried power rail

A semiconductor device, comprising:

• a protective liner on a support pillar;
• a buried power rail on a first portion of the protective liner, wherein the protective liner is on opposite sides of the buried power rail and wherein the buried power rail penetrates through the protective liner to make electrical contact with a backside interconnect;
• a source/drain on a second portion of the protective liner, wherein the support pillar is on an opposite side of the second portion of the protective liner from the source/drain and wherein the protective liner continuously extends on a top surface, a bottom surface, and a sidewall surface of the support pillar, wherein the first portion and the second portion of the protective liner have a same thickness;
• a plurality of nanochannels on the second portion of the protective liner, wherein the source/drain is in electrical contact with the plurality of nanochannels;
• and
• a source/drain contact on the source/drain and in electrical communication with the buried power rail.