US 12,772,805 B2 · Systems and methods of testing memory devices

Abstract

A memory device includes a first memory block. The first memory block includes a first memory sub-array and a first interface portion disposed next to the first memory sub-array. The first memory block further includes a plurality of first interconnect structures electrically coupled to the first memory sub-array through the first interface portion, and a second plurality of interconnect structures configured to electrically couple a corresponding one of the plurality of first interconnect structures to a transistor. The memory device further includes a first test structure and a second test structure disposed next to the first memory block, each configured to simulate electrical connections of the plurality of second interconnect structures. The first and second test structures are electrically coupled to each other and are each electrically isolated form the first memory block.

Claims20

Dependent claims

A memory device, comprising:

a memory block, including:
a memory array;
interface portions extending laterally through the memory array;
and
first interconnect structures extending vertically through the memory array and electrically coupled to the interface portions;
a first test structure;
and
a second test structure, the first test structure and the second test structure physically disposed next to the memory block, wherein:
the first test structure includes first test interconnect structures extending vertically;
the second test structure includes second test interconnect structures extending vertically and electrically coupled to the first test interconnect structures in series;
the first test structure and the second test structure are electrically isolated from the memory block;
and
the first test structure and the second test structure are configured to emulate the memory block.

10 more elements

A memory device, comprising:

a memory block, including:
a memory array;
interface portions extending laterally through the memory array;
and
first interconnect structures extending vertically through the memory array and electrically coupled to the interface portions, the first interconnect structures having a first profile;
and
a first test structure;
and
a second test structure, the first test structure and the second test structure physically disposed next to the memory block, wherein:
the first test structure includes first test interface portions having a second profile;
the second test structure electrically coupled to the first test structure in series, the second test structure including second test interface portions having a third profile;
the first test structure and the second test structure are electrically isolated from the memory block;
and
the first profile, the second profile, and the third profile each include a staircase configuration.

11 more elements

A memory device, comprising:

a memory block, including:
a memory array;
interface portions extending laterally through the memory array, the interface portions having a first staircase profile;
and
first interconnect structures extending vertically through the memory array and electrically coupled to the interface portions;
and
a first test structure;
and
a second test structure, the first test structure and the second test structure physically disposed next to the memory block, wherein:
the first test structure includes first test interconnect structures extending vertically;
the second test structure includes second test interconnect structures extending vertically and electrically coupled to the first test interconnect structures in series;
the first test structure and the second test structure are electrically isolated from the memory block;
and
the first test interconnect structures and the second test interconnect structures each emulate profiles and dimensions of the first interconnect structures.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application

18/678,953Filed 30 May 2024 · continuation

Priority

15 Nov 2021

Published

US 2024/0312850 A119 Sep 2024

Granted

20 Oct 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification6 codes

H10P 74/273
Structural arrangements therefor: interconnections for measuring or testing, e.g. probe pads
H10B 51/20
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the three-dimensional [3D] arrangements, e.g. with…
H10B 51/40
Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors: characterised by the peripheral circuit region
H10P 74/203
Characterised by the properties tested or measured, e.g. structural or electrical properties: structural properties, e.g. testing or measuring…

Family

Application17/526,774Parent of this division · filed 15 Nov 2021

Application18/232,518Parent of this continuation · filed 10 Aug 2023

US 11,854,914 B2Parent of this division · filed 26 Dec 2023

US 2024/0312850 A1Pre-grant publication · published 19 Sep 2024

US 12,020,996 B2Parent of this continuation

Application18/232,518Parent of this division

US 2023/0154806 A1Published application

US 2023/0386943 A1Published application

US 12,772,805 B2This patent

From the US filing history. Foreign family members aren’t listed.

Systems and methods of testing memory devices

Life of this patent

Systems and methods of testing memory devices

Life of this patent

Abstract

Claims20