US 12,772,592 B2 · Image sensor integrated chip structure

Abstract

The present disclosure relates to an image sensor integrated chip structure. The image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. A plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. The first substrate is bonded to the second substrate. A plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. A plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. The third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.

Claims20

Dependent claims

A method of forming an image sensor integrated chip structure, comprising:

bonding a first-side of a first substrate to a second-side of a second substrate, so that a first interconnect structure is between the first substrate and the second substrate;
forming a plurality of pixel support devices onto a first-side of the second substrate facing away from the first substrate;
forming a second interconnect structure onto the first-side of the second substrate;
forming a plurality of image sensing elements in a third substrate, wherein the third substrate comprises an isolation structure between neighboring ones of the plurality of image sensing elements and one or more floating diffusion nodes that are electrically interconnected and shared between the neighboring ones of the plurality of image sensing elements having the isolation structure therebetween;
forming a transfer gate onto a first-side of the third substrate;
forming a third interconnect structure, including interconnect wires and interconnect vias, on the first-side of the third substrate;
and
bonding the first-side of the third substrate to the first-side of the second substrate.

5 more elements

A method of forming an image sensor integrated chip structure, comprising:

forming one or more logic devices within a first substrate;
bonding a second substrate to the first substrate along a first bonding interface having a first plurality of metal regions and a first plurality of dielectric regions;
forming a plurality of pixel support devices along a surface of the second substrate that faces away from the first substrate;
forming a plurality of image sensing elements within pixel regions of a third substrate, the pixel regions respectively comprising two or more of the plurality of image sensing elements;
forming an isolation structure within the third substrate, the isolation structure wrapping around the pixel regions and extending between neighboring ones of the plurality of image sensing elements;
forming a first doped well region within the third substrate, wherein the first doped well region is arranged within an opening in the isolation structure that extends between the neighboring ones of the plurality of image sensing elements;
forming a plurality of transfer gates within the pixel regions of the third substrate;
and
bonding the second substrate to the third substrate along a second bonding interface having a second plurality of metal regions and a second plurality of dielectric regions.

6 more elements

A method of forming an image sensor integrated chip structure, comprising:

forming a plurality of pixel support devices onto a first-side of a first substrate, wherein the plurality of pixel support devices comprise a reset transistor, a source-follower transistor, and a row-select transistor;
forming a first interconnect structure onto the first-side of the first substrate;
forming a plurality of image sensing elements in a second substrate;
forming a plurality of transfer gates onto a first-side of the second substrate;
forming an isolation structure within the second substrate and wrapping around a pixel region comprising a plurality of image sensor regions, the plurality of image sensor regions respectively comprising one of the plurality of image sensing elements and one of the plurality of transfer gates;
performing an implantation process on the second substrate to form a floating diffusion region electrically coupled to the plurality of transfer gates within the plurality of image sensor regions;
wherein an opening laterally extends through the isolation structure, the opening being located at corners of four of the plurality of image sensor regions and the floating diffusion region being located within the opening;
forming a second interconnect structure, including interconnect wires and interconnect vias, on the first-side of the second substrate, the second interconnect structure being electrically coupled to the floating diffusion region;
and
bonding the first-side of the first substrate to the first-side of the second substrate.

7 more elements

Dependencies are inferred from the claim text.

Image sensor integrated chip structure

Life of this patent

Image sensor integrated chip structure

Life of this patent

Abstract

Claims20