Dielectric structure for small pixel designs

A method for forming an image sensor, the method comprising:

• forming a pair of photodetectors bordering in a semiconductor substrate;
• forming a pair of gate electrodes respectively overlying the pair of photodetectors;
• depositing a dielectric layer overlying the pair of gate electrodes and a boundary region between the pair of gate electrodes;
• forming a mask overlying the boundary region, between and laterally offset from the pair of gate electrodes;
• performing an etch into the dielectric layer with the mask in place to form a dielectric structure underlying the mask at the boundary region and to further form a pair of sidewall spacers respectively on sidewalls of the pair of gate electrodes;
• doping the semiconductor substrate with the dielectric structure in place to form a pair of floating diffusion nodes respectively bordering the pair of gate electrodes and outside the boundary region;
• and
• forming a trench isolation structure extending completely through the semiconductor substrate at the boundary region;
• wherein the dielectric layer extends along individual top surfaces of the pair of gate electrodes and the sidewalls of the pair of gate electrodes, wherein the etch clears the dielectric layer from the individual top surfaces of the pair of gate electrodes to expose the individual top surfaces of the pair of gate electrodes and concurrently forms the dielectric structure and the pair of sidewall spacers, and wherein the etch further forms the pair of sidewall spacers with a height greater than a height of the dielectric structure and from portions of the dielectric layer having individual top surfaces exposed at completion of the etch.

A method for forming an image sensor, the method comprising:

• forming a pair of photodetectors bordering in a semiconductor substrate;
• doping the semiconductor substrate to form a well region spaced from the pair of photodetectors;
• forming a pair of gate electrodes respectively overlying the pair of photodetectors and respectively on opposite sides of the well region;
• depositing a dielectric layer overlying the pair of gate electrodes and the well region;
• patterning the dielectric layer to form a dielectric structure between and spaced from the pair of gate electrodes;
• doping the semiconductor substrate with the dielectric structure in place to form a pair of floating diffusion nodes respectively bordering the pair of gate electrodes in the well region and separated from each other by a portion of the well region masked by the dielectric structure;
• and
• forming a pair of contact vias extending respectively to the pair of floating diffusion nodes with the dielectric structure in place, wherein the pair of contact vias are formed spaced from the dielectric structure, which is entirely formed before the pair of floating diffusion nodes are formed.