Insertion layer between channel and passivation for transistor

An integrated device, comprising:

• a gate overlying a substrate;
• a dielectric surrounding an upper surface and outer sidewalls of the gate;
• a channel layer surrounding upper surfaces and outer sidewalls of the dielectric;
• an insertion layer surrounding upper surfaces and outer sidewalls of the channel layer, wherein upper surfaces of the insertion layer comprise an uppermost surface directly over the gate and two additional upper surfaces terminating at outermost sidewalls of the insertion layer, wherein the two additional upper surfaces are at a substantially equal depth beneath the uppermost surface;
• a passivation layer surrounding the upper surfaces and outer sidewalls of the insertion layer, wherein the passivation layer and the dielectric extend past the outermost sidewalls of the insertion layer, and wherein the insertion layer separates an uppermost surface of the channel layer from the passivation layer;
• and
• source/drain contacts extending through the two additional upper surfaces to contact the channel layer and couple to source/drain regions in the channel layer, wherein the channel layer comprises an active region extending between the source/drain contacts, wherein the active region has a first concentration of a material from the passivation layer, and wherein an outer region of the channel layer at outermost sidewalls of the channel layer has a second concentration of the material from the passivation layer, where the second concentration is greater than the first concentration.

A method of forming an integrated device, comprising:

• forming a gate over an underlying layer;
• forming a dielectric over sidewalls and an upper surface of the gate and across the underlying layer;
• forming a channel layer over upper surfaces and sidewalls of the dielectric;
• forming an insertion layer over upper surfaces and sidewalls of the channel layer;
• forming a passivation layer covering the insertion layer, the channel layer, the gate, and the dielectric, wherein the passivation layer is formed using a physical vapor deposition process, and wherein ion bombardment from the physical vapor deposition process leads to diffusion of a material of the passivation layer into the insertion layer;
• etching contact openings through the passivation layer and the insertion layer, the contact openings extending to the channel layer;
• and
• forming source/drain contacts within the contact openings on opposite sides of the gate.