US 12,772,549 B2Granted

Semiconductor device with work function layer

AssigneeNanya Technology Corporation

InventorTse-Yao Huang

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Abstract

The present application discloses a semiconductor device. The semiconductor device includes a substrate; a peripheral gate structure including: a peripheral gate insulating layer inwardly positioned in the substrate and including a U-shaped cross-sectional profile, a peripheral work function layer positioned on the peripheral gate insulating layer and including a recess, a first peripheral interconnect layer positioned on the peripheral work function layer, a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer, and a peripheral capping layer positioned on the first peripheral interconnect layer. The peripheral work function layer includes titanium, titanium nitride, silicon, silicon germanium, or a combination thereof. The first peripheral liner layer includes graphene. The first peripheral interconnect layer includes tungsten, tungsten nitride, or a combination thereof.

Claims14

Dependent claims

A semiconductor device, comprising:

a substrate comprising an array area and a peripheral area;
an array gate structure positioned in the array area of the substrate;
and
a peripheral gate structure comprising:
a peripheral gate insulating layer inwardly positioned in the peripheral area of the substrate and comprising a U-shaped cross-sectional profile;
a peripheral work function layer positioned on the peripheral gate insulating layer and comprising a recess;
a first peripheral interconnect layer positioned on the peripheral work function layer;
a first peripheral liner layer positioned between the peripheral work function layer and the first peripheral interconnect layer;
a peripheral capping layer positioned on the first peripheral interconnect layer;
and
a second peripheral interconnector layer positioned between the first peripheral interconnect layer and the peripheral capping layer;
wherein a width of the peripheral gate structure is greater than two times a width of the array gate structure;
wherein the peripheral work function layer comprises titanium, titanium nitride, silicon, silicon germanium, or a combination thereof;
wherein the first peripheral liner layer comprises graphene;
and
wherein the first peripheral interconnect layer comprises tungsten, tungsten nitride, or a combination thereof;
wherein the array gate structure comprises:
an array gate insulating layer inwardly positioned in the array area of the substrate and comprising a U-shaped cross-sectional profile;
an array work function layer positioned on the array gate insulating layer;
a first array interconnector layer positioned on the array work function layer;
a first array liner layer positioned between the array work function layer and the first array interconnector layer:
a second array interconnector layer positioned on the first array interconnector layer;
a second array liner layer positioned between the second array interconnector layer and the first array interconnector layer;
and
an array capping layer positioned on the second array interconnector layer;
wherein a top surface of the array work function layer and a top surface of the peripheral work function layer are at different vertical levels.

23 more elements

A method for fabricating a semiconductor device, comprising:

providing a substrate comprising an array area and a peripheral area;
forming an array recess in the array area and forming a peripheral recess in the peripheral area;
conformally forming an array gate insulating layer in the array recess and conformally forming a peripheral gate insulating layer in the peripheral recess;
forming an array work function layer on the array gate insulating layer and forming a peripheral work function layer comprising a U-shaped cross-sectional profile on the peripheral gate insulating layer;
conformally forming a layer of first liner material on the array work function layer and on the peripheral work function layer;
forming a first array interconnector layer above the array work function layer and forming a first peripheral interconnect layer above the peripheral work function layer;
performing a liner removal process to turn the layer of first liner material into a first array liner layer between the first array interconnector layer and the array work function layer and into a first peripheral liner layer between the first peripheral interconnect layer and the peripheral work function layer;
forming an array capping layer on the first array interconnector layer and forming a peripheral capping layer on the first peripheral interconnect layer;
conformally forming a layer of second liner material on the first array interconnector layer and on the first peripheral interconnect layer;
forming a second array interconnector layer above the first array interconnector layer and forming a second peripheral interconnector layer above the first peripheral interconnect layer;
and
turning the layer of second liner material into a second array liner layer between the second array interconnector layer and the first array interconnector layer and into a second peripheral liner layer between the second peripheral interconnector layer and the first peripheral interconnect layer by the liner removal process;
wherein a width of the peripheral recess is greater than two times a width of the array recess.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/380,321Filed 16 Oct 2023 · division
Priority: 29 Dec 2022
Published: US 2024/0222370 A14 Jul 2024
Granted: 20 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 84/83
Of only field-effect components: of only insulated-gate FETs [IGFET]
H10D 64/513
Disposition of the gate electrodes, e.g. buried gates: within recesses in the substrate, e.g. trench gates, groove gates or buried gates
H10D 64/518
Characterised by the conducting layers: characterised by their lengths or sectional shapes
H10D 64/667
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor comprising a layer of…

Family

Application18/090,721Parent of this division · filed 29 Dec 2022
US 2024/0222371 A1Pre-grant publication · published 4 Jul 2024
US 12,408,421 B2Parent of this division
US 2024/0222370 A1Published application
US 12,772,549 B2This patent

From the US filing history. Foreign family members aren’t listed.

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