Forming metal gate cuts using multiple passes for depth control

An electronic device, comprising:

• a chip package comprising one or more dies, at least one of the one or more dies comprising one or more semiconductor regions above a dielectric fill and extending in a first direction between corresponding source regions and drain regions;
• a gate structure extending in a second direction over the one or more semiconductor regions;
• a first gate cut comprising a first dielectric material and extending in a third direction through an entire thickness of the gate structure, the first gate cut extending only partially into the dielectric fill;
• and
• a second gate cut comprising a second dielectric material and extending in the third direction through the entire thickness of the gate structure, the second gate cut extending only partially into the dielectric fill, wherein a width at a top of the second gate cut is at least 1.5× as large as a width at a top of the first gate cut, and wherein the first gate cut and the second gate cut each has a height in the third direction that differs by no more than 5 nm.

An integrated circuit comprising:

• a first semiconductor region above a dielectric fill and extending in a first direction between corresponding source and drain regions;
• a second semiconductor region above the dielectric fill and extending in the first direction between corresponding source and drain regions;
• a gate structure extending in a second direction over at least the first semiconductor region and the second semiconductor region;
• a first gate cut comprising a first dielectric material and extending in a third direction through an entire thickness of the gate structure, the first gate cut extending only partially into the dielectric fill;
• and
• a second gate cut comprising a second dielectric material and extending in the third direction through the entire thickness of the gate structure, the second gate cut extending only partially into the dielectric fill, wherein the first gate cut is adjacent to a first side of the first semiconductor region and is spaced in the second direction from the first side of the first semiconductor region by a first distance, and the second gate cut is adjacent to the corresponding first side of the second semiconductor region and is spaced in the second direction from the corresponding first side of the second semiconductor region by a second distance, the second distance differing by at least 4 nm from the first distance.