Integrated circuit device including a field-effect transistor having a semiconductor epitaxial structure and method of manufacturing the same

An integrated circuit device comprising:

• an insulating substrate including a plurality of fin structures extending in a first horizontal direction;
• a lower insulating layer covering top surfaces of the plurality of fin structures;
• a plurality of gate structures extending in a second horizontal direction crossing the first horizontal direction on the insulating substrate;
• and
• a first source/drain region and a second source/drain region spaced apart from each other in the first horizontal direction on the insulating substrate with a first gate structure of the plurality of gate structures disposed therebetween;
• and
• a semiconductor epitaxial structure disposed below a bottom surface of the lower insulating layer,
• wherein the first source/drain region penetrates the lower insulating layer and a portion of the semiconductor epitaxial structure, and contacts the semiconductor epitaxial structure;
• wherein a bottom surface of the semiconductor epitaxial structure is placed at a lower vertical level than a bottom surface of the first source/drain region, and both the bottom surface of the semiconductor epitaxial structure and the bottom surface of the first source/drain region are placed at lower vertical levels than a bottom surface of the lower insulating layer.

An integrated circuit device comprising:

• a rear wiring structure extending in a first horizontal direction;
• an insulating substrate disposed on the rear wiring structure and including a plurality of fin structures extending in the first horizontal direction;
• a lower insulating layer covering the plurality of fin structures;
• a plurality of gate structures extending in a second horizontal direction crossing the first horizontal direction on the insulating substrate;
• a plurality of nanosheet stacks disposed on the lower insulating layer and at least partially surrounded by the plurality of gate structures;
• a first source/drain region disposed on the insulating substrate and including a body portion and a vertical extension portion, wherein the body portion is disposed between the plurality of nanosheet stacks, and the vertical extension portion passes through the lower insulating layer and at least partially passes through a corresponding one of the plurality of fin structures;
• a second source/drain region spaced apart from the first source/drain region in the first horizontal direction with a first gate structure of the plurality of gate structures disposed therebetween;
• a semiconductor epitaxial structure at least partially surrounding the vertical extension portion of the first source/drain region;
• and
• a lower contact connecting the semiconductor epitaxial structure with the rear wiring structure;
• wherein a sidewall of the semiconductor epitaxial structure comprises:
• a first portion with a positive profile that extends to increase a width of the semiconductor epitaxial structure in the first horizontal direction as the sidewall of the semiconductor epitaxial structure moves away from a bottom surface of the lower insulating layer;
• and
• a second portion with a negative profile that extends to decrease the width of the semiconductor epitaxial structure in the first horizontal direction as the sidewall of the semiconductor epitaxial structure moves away from the bottom surface of the lower insulating layer.