Nanoribbon transistor source and drain with uniform nucleation
AssigneeIntel Corporation
InventorsShishir Pandya, James Kally, Robert Ehlert, Anand S. Murthy
Life of this patent
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Abstract
Described herein are nanoribbon transistors with a uniform layer of silicon material epitaxially deposited on the ends of the channel regions for the source and drain regions. The silicon is deposited over both the nanoribbon ends and dimple spacers between adjacent nanoribbons. The material may be deposited using a multicycle deposition and etch process, in which both crystalline and amorphous silicon are deposited in a low-selectivity process, and amorphous silicon is removed between deposition steps.
Claims20
An integrated circuit (IC) device comprising:
- a support structure;
- a plurality of elongated structures arranged in a stack, each elongated structure in the stack extending in a direction parallel to other elongated structures in the stack, each of the plurality of elongated structures having a first end and a second end opposite the first end;
- and
- a source or drain region coupled to the first ends of the plurality of elongated structures, the source or drain region comprising:
- a first layer comprising silicon substantially aligned along a (110) crystal plane, wherein less than 25% of the silicon in the first layer is aligned along a (111) crystal plane, and the silicon substantially aligned along the (110) crystal plane is a continuous layer over the first ends of the plurality of elongated structures and spacers between the first ends;
- and
- a second layer, the first layer between the first ends of the plurality of elongated structures and the second layer.
An integrated circuit (IC) device comprising:
- a support structure;
- a plurality of elongated structures arranged in a stack, each elongated structure in the stack extending in a direction parallel to other elongated structures in the stack, each of the plurality of elongated structures having a first end and a second end opposite the first end, the elongated structures comprising silicon;
- and
- a source or drain region coupled to the first ends of the plurality of elongated structures, the source or drain region comprising:
- a first layer comprising between 0.0001% and 2% germanium by weight;
- and
- a second layer comprising silicon and less than 0.0001% germanium by weight, wherein the first layer is between the first ends of the plurality of elongated structures and the second layer.
An integrated circuit (IC) device comprising:
- a first plurality of nanoribbons arranged in a first stack, each nanoribbon in the first stack extending in a direction parallel to other nanoribbons in the first stack;
- a second plurality of nanoribbons arranged in a second stack, each nanoribbon in the second stack extending in a direction parallel to nanoribbons in the first stack and to other nanoribbons in the second stack;
- and
- a source or drain region between the first plurality of nanoribbons and the second plurality of nanoribbons, the source or drain region having a first layer comprising silicon coupled to the first plurality of nanoribbons, a second layer coupled to the second plurality of nanoribbons, and a third layer between the first layer and the second layer;
- wherein the first layer is a continuous layer over the first plurality of nanoribbons and spacers between the first plurality of nanoribbons, less than 25% of the silicon in the first layer is aligned along a (111) crystal plane, and the first layer has a thickness variation in the direction parallel to the nanoribbons in the first stack of less than 2 nanometers.
Dependencies are inferred from the claim text.