Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches

An integrated circuit structure, comprising:

• a vertical arrangement of nanowires, wherein all nanowires of the vertical arrangement of nanowires are oxide nanowires;
• a gate stack over the vertical arrangement of nanowires, around each of the oxide nanowires, wherein the gate stack comprises a conductive gate electrode;
• and
• an interconnect structure below the vertical arrangement of nanowires, wherein a conductive via of the interconnect structure is in contact with a bottom surface of the conductive gate electrode.

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a first vertical arrangement of nanowires and a second vertical arrangement of nanowires, the first vertical arrangement of nanowires having an active uppermost nanowire and an oxide bottommost nanowire, the second vertical arrangement of nanowires having an oxide uppermost nanowire and an active bottommost nanowire, and the first and second vertical arrangements of nanowires having co-planar uppermost nanowires and co-planar bottommost nanowires;
• a first gate structure over the first vertical arrangement of nanowires;
• and
• a second gate structure over the second vertical arrangement of nanowires and around the oxide bottommost nanowire.