Integrated circuit structure and manufacturing method thereof

A method comprising:

• depositing a stacking structure over a substrate, wherein the stacking structure comprises first semiconductor layers and second semiconductor layers alternately arranged;
• forming a mask layer over the stacking structure, wherein the mask layer comprises:
• a first hard mask extending in a first direction and having a first width in a second direction different from the first direction in a top view;
• a second hard mask extending in the first direction and having a second width greater than the first width in the second direction in the top view;
• and
• a third hard mask interconnecting the first hard mask and the second hard mask and having a third width different from the first width and the second width in the second direction in the top view;
• patterning the stacking structure by using the mask layer as an etch mask to form a first fin structure patterned from the first hard mask, a second fin structure patterned from the second hard mask, and a third fin structure patterned from the third hard mask;
• forming a dielectric fin on a sidewall of the first fin structure and a sidewall of the third fin structure, wherein sidewalls of the second fin structure are uncovered by the dielectric fin;
• forming a first isolation structure on another sidewall of the first fin structure;
• forming second isolation structures on the sidewalls of the second fin structure;
• forming a first transistor over the first fin structure, wherein the second semiconductor layers in the first fin structure are channel layers of the first transistor;
• and
• forming a second transistor over the second fin structure, wherein the second semiconductor layers in the second fin structure are channel layers of the second transistor.

A method comprising:

• depositing a stacking structure over a substrate, wherein the stacking structure comprises first semiconductor layers and second semiconductor layers alternately arranged;
• patterning the stacking structure to form a first fin structure extending in a first direction, a second fin structure extending in the first direction in a top view, and a third fin structure interconnecting the first fin structure and the second fin structure, wherein the first fin structure, the third fin structure, and the second fin structure are arranged in the first direction and have different widths in a second direction different from the first direction in the top view, and a sidewall of the third fin structure is substantially aligned with a sidewall of the first fin structure and is misaligned with a sidewall of the second fin structure;
• forming a first transistor over the first fin structure, wherein the second semiconductor layers in the first fin structure are channel layers of the first transistor;
• forming a second transistor over the second fin structure, wherein the second semiconductor layers in the second fin structure are channel layers of the second transistor;
• and
• forming a dielectric gate structure between the second fin structure and the third fin structure after forming the second transistor.