Semiconductor device having reduced risk of dielectric breakdown

A semiconductor device comprising a semiconductor substrate, wherein

• the semiconductor substrate has:
• an active portion;
• a circumferential well region surrounding the active portion;
• a plurality of gate trench portions provided in the active portion on an upper surface of the semiconductor substrate and extending along an extending direction;
• and
• a plurality of dummy trench portions provided in the active portion on the upper surface of the semiconductor substrate and extending along the extending direction, the semiconductor device further comprising:
• a gate runner provided between the active portion and an end side of the semiconductor substrate, the gate runner having a portion extending in a direction perpendicular to the extending direction in top view;
• and
• a plurality of gate polysilicon disposed apart from each other and distributed along the portion of the gate runner extending in the direction perpendicular to the extending direction in top view and each of the plurality of gate polysilicon connecting one or more corresponding gate trench portions of the plurality of gate trench portions to the gate runner, wherein
• a distance in the extending direction from each of the plurality of dummy trench portions to the portion of the gate runner extending in the direction perpendicular to the extending direction in top view is longer than a distance in the extending direction from each of the plurality of gate trench portions to the portion of the gate runner extending in the direction perpendicular to the extending direction in top view,
• each of the plurality of gate polysilicon has a lower surface, and
• in a depth direction of the semiconductor substrate, a lower surface of the gate runner is farther from the upper surface of the semiconductor substrate than the lower surface of each of the plurality of gate polysilicon.