Memory cell and manufacturing method thereof, three-dimensional memory and operation method thereof

A method of manufacturing a memory cell, comprising:

• forming a stack on a substrate;
• forming a plurality of channel holes in the stack and a part of the substrate, and etching at least one sacrificial layer in the stack formed with the plurality of channel holes to form a ring-shaped limiting component;
• forming a gate dielectric layer, a channel layer and a variable resistance layer sequentially on a surface of each channel hole for which the ring-shaped limiting component is formed by etching;
• filling an insulator material layer inside each channel hole without the material layer therein;
• forming a bit line lead-out end on a part of a top of the channel layer;
• and
• etching the sacrificial layer in the stack, and replacing the sacrificial layer with a second stack material layer,
• wherein a gate voltage applied to at least one second stack material layer and a pulse signal applied to a bit line connected to the channel layer are controlled to change a resistance state of the variable resistance layer, so as to enable the memory cell to perform a reading operation, a writing operation or an erasing operation on the variable resistance layer.