Three-dimensional memory device, having bridge structure, and methods for forming the same

A three-dimensional (3D) memory device, comprising:

• a memory array structure comprising a first memory array structure and a second memory array structure each comprising a plurality of conductive/dielectric layer pairs;
• and
• a staircase structure arranged between the first memory array structure and the second memory array structure in a first lateral direction and comprising a first staircase zone and a second staircase zone arranged in a second lateral direction perpendicular to the first lateral direction, the first staircase zone being adjacent to the second staircase zone in the second lateral direction,
• wherein:
• the first staircase zone comprises a first staircase and a second staircase each comprising a plurality of stairs;
• the second staircase zone comprises a bridge structure and a plurality of staircases over the bridge structure, the bridge structure being configured to connect the first memory array structure and the second memory array structure;
• one stair of the first staircase, away from the second memory array structure, is connected with the second memory array structure through the bridge structure of the second staircase zone;
• the first staircase faces and is aligned with the second staircase in the first lateral direction;
• and
• in a vertical direction perpendicular to the first and second lateral directions, each stair of the first staircase is positioned at a depth different from any stair of the second staircase facing the first staircase, and a highest stair in the first staircase is lower than a highest conductive/dielectric portion pair of the second staircase by one conductive/dielectric pair.

A three-dimensional (3D) memory device, comprising:

• a memory array structure comprising a first memory array structure and a second memory array structure each comprising a plurality of conductive/dielectric layer pairs;
• and
• a staircase structure arranged between the first memory array structure and the second memory array structure in a first lateral direction and comprising a first staircase zone and a second staircase zone arranged in a second lateral direction perpendicular to the first lateral direction, the first staircase zone being adjacent to the second staircase zone in the second lateral direction,
• wherein:
• the first staircase zone comprises a first staircase and a second staircase each comprising a plurality of stairs, the first staircase facing and being aligned with the second staircase in the first lateral direction;
• the second staircase zone comprises a bridge structure and a plurality of staircases over the bridge structure, the bridge structure being configured to connect the first memory array structure and the second memory array structure, one staircase of the plurality of staircases of the second staircase zone being adjacent to one of the first staircase and the second staircase in the second lateral direction;
• one stair of the first staircase, away from the second memory array structure, is connected with the second memory array structure through the bridge structure of the second staircase zone, the one stair of the first staircase extends in the second lateral direction to be connected to a corresponding conductive portion of the bridge structure in the second staircase zone;
• and
• in a vertical direction perpendicular to the first and second lateral directions, each stair of the first staircase is positioned at a depth different from any stair of the second staircase facing the first staircase, and the plurality of stairs of the first staircase and the plurality of stairs of the second staircase are arranged at alternating vertical levels in a vertical direction perpendicular to the first lateral direction and the second lateral direction.