Memory device and method of fabricating the same

A memory device, comprising:

• a substrate, comprising an array region, a peripheral region, and a transition region, wherein the transition region is located between the array region and the peripheral region;
• a plurality of word line structures, disposed in the substrate and extending along a first direction from the array region to the transition region;
• a dielectric layer, disposed above the substrate;
• a plurality of bit line structures, disposed in the dielectric layer and extending along a second direction from the array region to the transition region;
• a plurality of partition walls, disposed above the plurality of bit line structures and in the dielectric layer, and extending along the first direction from the array region to the transition region;
• a plurality of dummy partition walls, extending along the first direction, covering at least ends of the plurality of bit line structures, and located in the dielectric layer;
• and
• a plurality of conductive plugs, located between the adjacent dummy partition walls, wherein each of the plurality of conductive plugs is electrically connected to one of the plurality of bit line structures.

A method of fabricating a memory device, comprising:

• providing a substrate, wherein the substrate comprises an array region, a peripheral region, and a transition region, and the transition region is located between the array region and the peripheral region;
• forming a plurality of word line structures in the substrate, wherein the plurality of word line structures extends along a first direction from the array region to the transition region;
• forming a dielectric layer on the substrate;
• forming a plurality of bit line structures in the dielectric layer, wherein the plurality of bit line structures extends along a second direction from the array region to the transition region;
• forming a plurality of partition walls above the plurality of bit line structures and in the dielectric layer, wherein the plurality of partition walls extend along the first direction from the array region to the transition region;
• forming a plurality of dummy partition walls in the dielectric layer, wherein the plurality of dummy partition walls extend along the first direction and cover at least ends of the plurality of bit line structures;
• forming a plurality of conductive plug openings in the dielectric layer between the plurality of adjacent dummy partition walls;
• and
• forming a plurality of conductive plugs in the plurality of conductive plug openings, wherein each of the plurality of conductive plugs is electrically connected to one of the plurality of bit line structures.