US 12,772,437 B2Granted

Semiconductor device having a buffer structure

AssigneeSamsung Electronics Co., Ltd.

InventorsAhrang Choi, Chansic Yoon, Hoin Ryu, Junghoon Han

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device includes active regions defined by a device isolation region in a substrate; trenches extending in a first direction to intersect the active regions; buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions; a buffer structure covering the active regions, the isolation region, and the buried gate structures; bit line structures extending in a second direction intersecting the first direction on the active regions and connected to the active regions; storage node contacts between the bit line structures, penetrating through the buffer structure and in contact with the active regions; and capacitor structures in contact with an upper surface of the storage node contacts.

Claims20

Dependent claims

A semiconductor device, comprising:

active regions defined by a device isolation region in a substrate;
trenches extending lengthwise in a first direction to intersect the active regions;
buried gate structures buried in the trenches, respectively, and having upper surfaces located on a level lower than a level of upper surfaces of the active regions;
a buffer structure covering the active regions, the device isolation region, and the buried gate structures;
bit line structures extending lengthwise in a second direction intersecting the first direction on the active regions and connected to the active regions;
spacer structures that cover sidewalls of the bit line structures and are disposed on the buffer structure;
storage node contacts between the bit line structures, penetrating through the buffer structure and in direct contact with the active regions;
and
capacitor structures in direct contact with an upper surface of the storage node contacts,
wherein the buffer structure includes:
a first buffer pattern extending along profiles of the upper surfaces of the active regions, the device isolation region, and the buried gate structures and having an upper surface including concave portions;
a second buffer pattern including at least first portions filling the concave portions of the upper surface of the first buffer pattern, the second buffer pattern being in direct contact with the first pattern;
and
a third buffer pattern on the first buffer pattern and the second buffer pattern, the third buffer pattern being in direct contact with the second buffer pattern,
wherein each of the bit line structures includes a first portion on an upper surface of the buffer structure and second portions penetrating through the buffer structure,
wherein a lowermost portion of a lower surface of the second buffer pattern is at a vertical level farther away from a lower surface of the substrate in a third direction than a vertical level of a lowermost portion of a lower surface of the first buffer pattern, the third direction being perpendicular to the first and second directions,
wherein an uppermost portion of an upper surface of the second buffer pattern is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern,
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate,
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction,
wherein the spacer structures are in contact with side surfaces of the first portion of the bit line structure, and
wherein the third buffer pattern is in direct contact with a lower surface of the first portion of the bit line structure.

18 more elements

A semiconductor device, comprising:

active regions defined by a device isolation region in a substrate;
buried gate structures intersecting the active regions;
word lines buried in the substrate, extending lengthwise in a first direction, and located on a level lower than a level of upper surfaces of the active regions;
capping patterns buried in the substrate, located on the word lines, and having upper surfaces located on a level lower than a level of the upper surfaces of the active regions;
a buffer structure on the device isolation region, the active regions, and the capping patterns;
bit line structures extending lengthwise in a second direction intersecting the first direction on the active regions and connected to the active regions;
and
spacer structures that cover sidewalls of the bit line structures and are disposed on the buffer structure,
wherein each of the bit line structures includes a first portion on an upper surface of the buffer structure and second portions penetrating through the buffer structure,
wherein the buffer structure includes a first region on the active regions and the device isolation region, and a second region on the capping patterns,
wherein the first region has a first thickness,
wherein the second region has a second thickness greater than the first thickness,
wherein the buffer structure includes:
a first buffer pattern extending along profiles of the upper surfaces of the active regions, the device isolation region, and the buried gate structures and having an upper surface including concave portions;
a second buffer pattern including at least first portions filling the concave portions of the upper surface of the first buffer pattern;
and
a third buffer pattern that is on and in direct contact with the first buffer pattern, and below and in direct contact with the second buffer pattern,
wherein a lowermost portion of a lower surface of the second buffer pattern is at a vertical level farther away from a lower surface of the substrate in a third direction than a vertical level of a lowermost portion of a lower surface of the first buffer pattern, the third direction being perpendicular to the first and second directions,
wherein an uppermost portion of an upper surface of the second buffer pattern is at a vertical level farther away from the lower surface of the substrate in the third direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern,
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate,
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the third direction, and
wherein the second buffer pattern is in direct contact with a lower surface of the first portion of the bit line structure.

19 more elements

A semiconductor device, comprising:

an isolation region defining an active region within a substrate;
buried gate structures intersecting the active region, extending lengthwise into the isolation region, and having upper surfaces located on a level lower than a level of an upper surface of the active region;
a first buffer pattern on the buried gate structures and the isolation region, and having an upper surface including concave portions on the buried gate structures;
a second buffer pattern filling the concave portions of the upper surface of the first buffer pattern and including at least first portions vertically overlapping the buried gate structures;
a bit line structure on the active region and connected to the active region;
and
spacer structures that cover sidewalls of the bit line structure and are disposed on the second buffer pattern,
wherein the bit line structure includes a first portion on an upper surface of the second buffer pattern and a second portion penetrating through the first and second buffer patterns,
wherein the second buffer pattern is in direct contact with the first buffer pattern,
wherein a lowermost portion of a lower surface of the second buffer pattern is at a vertical level farther away from a lower surface of the substrate in a vertical direction than a vertical level of a lowermost portion of a lower surface of the first buffer pattern, the vertical direction being perpendicular to a horizontal upper surface of the isolation region,
wherein an uppermost portion of an upper surface of the second buffer pattern is at a vertical level farther away from the lower surface of the substrate in the vertical direction than a vertical level of an uppermost portion of the upper surface of the first buffer pattern,
wherein the lowermost portions of the lower surfaces of the first and second buffer patterns face the substrate,
wherein the uppermost portions of the upper surfaces of the first and second buffer patterns face away from the substrate in the vertical direction, and
wherein the second buffer pattern is in direct contact with a lower surface of the first portion of the bit line structure.

11 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/880,723Filed 4 Aug 2022
Priority: KR 10-2021-018799827 Dec 2021
Published: US 2023/0209808 A129 Jun 2023
Granted: 20 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10B 12/34
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: the transistor being at least partially in a trench in the substrate
H10B 12/053
Making the transistor: the transistor being at least partially in a trench in the substrate
H10B 12/315
Having a storage electrode stacked over the transistor: with the capacitor higher than a bit line
H10B 12/48
DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells: data lines or contacts therefor

Family

US 2023/0209808 A1Pre-grant publication · published 29 Jun 2023
US 12,772,437 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key