Wafer placement table
AssigneeNGK Insulators, Ltd.
InventorsHiroya Sugimoto, Masaki Ishikawa
Life of this patent
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AssigneeNGK Insulators, Ltd.
InventorsHiroya Sugimoto, Masaki Ishikawa
Estimating the term…
A wafer placement table includes a ceramic base having a wafer placement surface; resistance heating elements buried in the ceramic base; jumper layers having a planar shape and provided in a different layer from the resistance heating elements; an inner via connecting the jumper layer and an end of the resistance heating element; and a feed via connected to the jumper layer, wherein each of the resistance heating elements is provided for each of zones of a surface parallel to the wafer placement surface, each of the jumper layers is provided for each of the resistance heating elements, and a center-to-center distance between the inner via and the feed via in each of the jumper layers is greater than or equal to 50 mm.
A wafer placement table comprising:
Dependencies are inferred from the claim text.