Analog-to-digital converter and image sensor including the same

An image sensor comprising:

• a pixel array including a plurality of pixels;
• a plurality of column lines configured to output pixel voltages of the plurality of pixels;
• a plurality of comparators connected to each of the plurality of column lines, and each configured to generate a comparison signal based on a ramp signal and a pixel voltage;
• and
• a plurality of counter circuits configured to receive the comparison signal from each of the plurality of comparators and output a count value corresponding to the pixel voltage based on the comparison signal,
• wherein each of the plurality of counter circuits includes:
• a first latch circuit configured to latch a gray code;
• a second latch circuit configured to latch a first binary code among outputs of the first latch circuit;
• a most significant bit counter circuit configured to receive an output of a most significant bit among the outputs of the first latch circuit and count high-order n bits of the count value, wherein the n is an integer of 1 or more;
• and
• an arithmetic unit configured to perform an operation on a second binary code among the outputs of the first latch circuit and the first binary code,
• wherein the gray code corresponds to lower-order m bits of the count value, wherein the m is an integer of 1 or more, and
• wherein the most significant bit counter circuit is arranged such that a first distance between the first latch circuit and the most significant bit counter circuit is smaller than a second distance between the first latch circuit and the second latch circuit.

An image sensor comprising:

• a pixel array including a plurality of pixels, each pixel configured to output a pixel signal;
• and
• an analog-to-digital converter configured to convert the pixel signal into pixel data,
• wherein the analog-to-digital converter comprises:
• a comparator configured to generate a comparison signal based on a ramp signal and an input signal;
• and
• a counter circuit configured to receive a counting code and the comparison signal and output a count value corresponding to a magnitude of the input signal based on the comparison signal,
• wherein the counter circuit includes:
• a first counter circuit including a plurality of latch circuits and an adder, and the first counter circuit configured to:
• latch the counting code, and
• generate least significant bit signals of the count value;
• and
• a second counter circuit configured to generate most significant bit signals sequentially toggling in response to one of the least significant bit signals or an inversion signal of the one of the least significant bit signals, and
• wherein the plurality of latch circuits, the adder, and the second counter circuit are arranged in series, and the second counter circuit is arranged between the plurality of latch circuits.