US 12,771,348 B1Granted

Transmitter circuit for low power application

AssigneeCadence Design Systems, Inc.

InventorVinod Kumar

Life of this patent

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Abstract

Embodiments included herein are directed towards a circuit and method of using the same. The transmitter circuit may include a process, voltage, temperature (PVT) controlled pull-up pre-driver and a PVT controlled pull-up driver. The transmitter circuit may further include a PVT controlled pull-down pre-driver and a PVT controlled pull-down driver. The transmitter circuit may also include a thin oxide hybrid static switch operatively connected with the PVT controlled pull-up pre-driver and the PVT controlled pull-up driver. The transmitter circuit may further include a thin oxide NMOS static switch operatively connected with the PVT controlled pull-down pre-driver and the PVT controlled pull-down driver.

Claims16

Dependent claims

A transmission method comprising:

providing a process, voltage, temperature (PVT) controlled pull-up pre-driver and a process, voltage, temperature (PVT) controlled pull-up driver;
providing a process, voltage, temperature (PVT) controlled pull-down pre-driver and a process, voltage, temperature (PVT) controlled pull-down driver;
operatively connecting a thin oxide hybrid static switch with the PVT controlled pull-up pre-driver and the PVT controlled pull-up driver;
and
operatively connecting a thin oxide NMOS static switch with the PVT controlled pull-down pre-driver and the PVT controlled pull-down driver wherein the PVT controlled pull-up pre-driver and the PVT controlled pull-up driver includes a first NMOS pull-up driver calibration portion, which is calibrated first;
and
wherein the PVT controlled pull-up pre-driver and the PVT controlled pull-up driver includes a PMOS pull-up driver calibration portion located after the NMOS pull-up calibration portion, which is calibrated after NMOS pull-up calibration code is saturated.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/941,270Filed 8 Nov 2024
Granted: 20 Oct 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H03K 19/00384
Modifications for compensating variations of temperature, supply voltage or other physical parameters: in field effect transistor circuits
G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
H03K 19/01742
In synchronous circuits, i.e. by using clock signals: by means of a pull-up or down element
H03K
Pulse technique

Family

No related US applications are recorded in the indexed filing history.

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