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US 12,771,333 B2Granted
Comparator and semiconductor apparatus using the same
AssigneeSK hynix Inc.
InventorsChang Hyun Pyo, Hyun Kyu Park, Dong Wook Jang
Life of this patent
Estimating the term…
Abstract
A comparator includes an amplification circuit and a latch circuit. The amplification circuit generates a first amplification signal and a second amplification signal based on a clock signal, an input signal, and a reference voltage. The latch circuit generates a first output signal and a second output signal based on the clock signal, the first amplified signal, and the second amplified signal.
Claims25
A comparator comprising:
- an amplification circuit configured to generate a first amplified signal and a second amplified signal by differentially amplifying an input signal and a reference voltage when a clock signal is at a first logic level and to reset the first amplified signal and the second amplified signal when the clock signal is at a second logic level;
- and
- a latch circuit configured to generate a first output signal and a second output signal based on the first amplified signal and the second amplified signal when the clock signal is at the first logic level and to reset the first output signal and the second output signal when the clock signal is at the second logic level;
- wherein the amplification circuit comprises:
- a first amplification node and a second amplification node that are coupled to a first power supply voltage based on the clock signal;
- a first transistor coupled to a second power supply voltage and configured to receive the input signal;
- a second transistor configured to couple the first amplification node to the first transistor based on the clock signal;
- a third transistor coupled to the second power supply voltage and configured to receive the reference voltage;
- and
- a fourth transistor configured to couple the second amplification node and the third transistor based on the clock signal;
- and
- wherein the first amplified signal is output on the first amplification node, and the second amplified signal is output on the second amplification node.
9 more elements
A comparator comprising:
- an amplification circuit configured to generate a first amplified signal and a second amplified signal by differentially amplifying an input signal and a reference voltage when a clock signal is at a first logic level and to reset the first amplified signal and the second amplified signal when the clock signal is at a second logic level;
- and
- a latch circuit configured to generate a first output signal and a second output signal based on the first amplified signal and the second amplified signal when the clock signal is at the first logic level and to reset the first output signal and the second output signal when the clock signal is at the second logic level;
- wherein the amplification circuit comprises:
- a first amplification node and a second amplification node coupled to a first power supply voltage based on the clock signal;
- a first transistor coupled to a second power supply voltage and configured to receive the input signal;
- a second transistor configured to couple the first amplification node and the first transistor based on the clock signal;
- a third transistor coupled to the second power supply voltage and configured to receive the reference voltage;
- a fourth transistor configured to couple the second amplification node and the third transistor based on the clock signal;
- a first compensation circuit configured to change a voltage level at the first amplification node based on the reference voltage;
- and
- a second compensation circuit configured to change a voltage level at the second amplification node based on the input signal;
- and
- wherein the first amplified signal is output on the first amplification node, and the second amplified signal is output on the second amplification node.
11 more elements
A comparator comprising:
- an amplification circuit configured to generate a first amplified signal and a second amplified signal by differentially amplifying an input signal and a reference voltage when a clock signal is at a first logic level and to reset the first amplified signal and the second amplified signal when the clock signal is at a second logic level;
- and
- a latch circuit configured to generate a first output signal and a second output signal based on the first amplified signal and the second amplified signal when the clock signal is at the first logic level and to reset the first output signal and the second output signal when the clock signal is at the second logic level;
- wherein the amplification circuit comprises:
- a first input circuit configured to decrease a voltage level at a first amplification node when the input signal is at or above a first voltage level and output the first amplified signal on the first amplification node;
- a second input circuit configured to decrease a voltage level at a second amplification node when the reference voltage is at or above the first voltage level and output the second amplified signal on the second amplification node;
- a first compensation circuit configured to decrease the voltage level at the first amplification node when the reference voltage is at or below a second voltage level;
- and
- a second compensation circuit configured to decrease the voltage level at the second amplification node when the input signal is at or below the second voltage level.
6 more elements
An amplification circuit comprising:
- a first input circuit configured to change a voltage level at an amplification node when an input signal is at or above a first voltage level, such that a first amplified signal is output on the first amplification node;
- a second input circuit configured to change a voltage level at a second amplification node when a reference voltage is at or above a first voltage level, such that a second amplified signal is output on the second amplification node;
- a first compensation circuit configured to decrease a voltage level at the first amplification node when the reference voltage is at or below a second voltage level;
- and
- a second compensation circuit configured to decrease the voltage level at the second amplification node when the input signal is at or below the second voltage level.
2 more elements
Dependencies are inferred from the claim text.