Serial interface bus with glitch filtering

A non-transitory computer-readable medium storing a set of instructions for filtering glitches in a serial interface bus, the set of instructions comprising:

• one or more instructions that, when executed by one or more processors of a device, cause the device to:
• receive, by a glitch filter associated with a serial interface bus, an input signal associated with a glitch;
• reject, by the glitch filter, the glitch based at least in part on a plurality of state machine transitions associated with the glitch filter and a set of timers associated with the glitch filter, wherein the set of timers includes a high timer and a low timer, and the input signal is locked at a high state for at least a length of the high timer and the input signal is locked at a low state for at least a length of the low timer, in accordance with the plurality of state machine transitions;
• and
• provide, by the glitch filter, an output signal based at least in part on the plurality of state machine transitions and the set of timers.

An apparatus for filtering glitches in a serial interface bus, comprising:

• means for receiving an input signal associated with a glitch by a glitch filter;
• means for rejecting, by the glitch filter, the glitch based at least in part on a plurality of state machine transitions and a set of timers associated with the glitch filter, wherein the set of timers includes a high timer and a low timer, and the input signal is locked at a high state for at least a length of the high timer and the input signal is locked at a low state for at least a length of the low timer, in accordance with the plurality of state machine transitions;
• and
• means for providing, by the glitch filter, an output signal based at least in part on the plurality of state machine transitions and the set of timers.