Duty-cycle and stray capacitance insensitive switched-capacitor current source

A method of sourcing a current from a switched-capacitor current source, comprising:

• sourcing the current from a common node to charge a first capacitor coupled between the common node and a ground in a first switched-capacitor resistor to a reference voltage during a first phase of a clock signal;
• sourcing the current from the common node to charge a second capacitor coupled between the common node and a ground in a second switched-capacitor resistor to the reference voltage during a second phase of the clock signal;
• and
• mirroring the current to form a bias current of the switched-capacitor current source.

A switched-capacitor current source, comprising:

• a first switched-capacitor resistor including a first capacitor having a top plate configured to be charged to a first reference voltage during a charging clock phase of a first clock signal;
• a first shielding line adjacent the top plate of the first capacitor between the top plate and grounded signal nodes of the switched-capacitor current source, wherein the first shielding line is configured to be charged during the charging clock phase of the first clock signal;
• a differential amplifier;
• a first switch coupled between the first shielding line and an output terminal of the differential amplifier;
• and
• a second switch coupled between the first shielding line and ground.

A switched-capacitor current source, comprising:

• a first transistor having a source coupled to a power supply node for a power supply voltage;
• a first switch coupled to a drain of the first transistor;
• a first switched-capacitor resistor including a first capacitor, wherein the capacitance of the first capacitor is proportional to a capacitance of an integration capacitor in a continuous-time integration stage of an analog-to-digital converter, the first switched-capacitor resistor being configured to couple a first plate of the first capacitor to the first switch to charge the first capacitor from the power supply node during a charging clock phase of a first clock signal, wherein a second plate of the first capacitor is coupled to ground during the charging clock phase;
• a second switch coupled to the drain of the first transistor;
• and
• a second switched-capacitor resistor including a second capacitor, wherein a capacitance of the first capacitor equals a capacitance of the second capacitor, the second switched-capacitor resistor being configured to couple a first plate of the second capacitor to the second switch to charge the second capacitor from the power supply node during a charging clock phase of a second clock signal, wherein a second plate of the second capacitor is coupled to ground during the charging clock phase,
• wherein the analog-to-digital converter includes a tuning circuit including a variable tuning resistor configured to be charged by a mirrored version of a charging current conducted by the first transistor.