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US 12,771,232 B2Granted
High voltage switch design in a low voltage process node with small quiescent current
AssigneeQUALCOMM Incorproated
InventorShamim Ahmed
Life of this patent
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Abstract
A system-on-chip (SoC) is described. The SoC includes an interface physical input/output (IO) module (PHY) on a substrate. The interface PHY includes a high voltage power rail and a low voltage power rail. The SoC also includes a voltage regulator on the substrate and configured to supply to a low voltage to the low voltage power rail. The SoC further includes a high voltage switch on the substrate and coupled to the high voltage power rail of the interface PHY and the voltage regulator. The high voltage switch to maintain a quiescent current in the interface PHY below an activation current level.
Claims18
A system-on-chip (SoC) comprising:
- an interface physical input/output (IO) module (PHY) on a substrate, the interface PHY having a high voltage power rail and a low voltage power rail;
- a voltage regulator on the substrate and configured to supply to a low voltage to the low voltage power rail;
- a high voltage switch on the substrate and coupled to the high voltage power rail of the interface PHY and the voltage regulator, the high voltage switch configured to maintain a quiescent current in the interface PHY below an activation current level;
- and
- a gate driver circuit coupled to a gate and a source of the high voltage switch, the gate driver circuit comprising:
- a resistor divider including a pull-up resistor coupled between the source and the gate of the high voltage switch, a first pull-down resistor and a second pull-down resistor, the first pull-down resistor coupled between the pull-up resistor and the second pull-down resistor;
- and
- first cascaded transistors coupled to the second pull-down resistor.
5 more elements
A system-on-chip (SoC) comprising:
- an interface physical input/output (IO) module (PHY) on a substrate, the interface PHY having a high voltage power rail and a low voltage power rail;
- a voltage regulator on the substrate and configured to supply to a low voltage to the low voltage power rail;
- and
- a high voltage switch on the substrate and coupled to the high voltage power rail of the interface PHY and the voltage regulator, the high voltage switch configured to maintain a quiescent current in the interface PHY below an activation current level;
- a disable pull-down circuit, comprising a pull-down resistor, a first transistor, a second transistor, and a source degeneration resistor, coupled in series;
- and
- an enable pull-down (EN_PD) signal coupled to the first transistor and/or the second transistor to provide a low impedance path for a gate node of the high voltage switch to maintain the high voltage switch in an off state.
4 more elements
A system-on-chip (SoC) comprising:
- an interface physical input/output (IO) module (PHY) on a substrate, the interface PHY having a high voltage power rail and a low voltage power rail;
- a voltage regulator on the substrate and configured to supply to a low voltage to the low voltage power rail;
- and
- a high voltage switch on the substrate and coupled to the high voltage power rail of the interface PHY and the voltage regulator, the high voltage switch configured to maintain a quiescent current in the interface PHY below an activation current level;
- a no-supply pull-down circuit comprising an N-type transistor, a P-type transistor, and a pull-down resistor coupled in series between an output voltage node and a ground node;
- and
- a control supply coupled to the P-type transistor to turn-off the P-type transistor and disable a current path between the output voltage node and the ground node.
4 more elements
A method to perform a power up sequence, the method comprising:
- receiving a master input voltage at an input of a high voltage switch coupled to a high voltage power rail of an input/output (IO) interface;
- supplying, by a voltage regulator, a low output voltage to a low voltage power rail of the IO interface;
- maintaining a quiescent current in the IO interface at a level below an activation current level when the master input voltage is applied to the high voltage switch by:
- shorting, in response to an enable signal, a gate and a source of the high voltage switch;
- and
- initiating a soft start of the high voltage switch;
- and
- directly supplying, using the high voltage switch, the master input voltage to the high voltage power rail of the IO interface to maintain the power up sequence of the IO interface.
5 more elements
A method to perform a power up sequence, the method comprising:
- receiving a master input voltage at an input of a high voltage switch coupled to a high voltage power rail of an input/output (IO) interface;
- supplying, by a voltage regulator, a low output voltage to a low voltage power rail of the IO interface;
- maintaining a quiescent current in the IO interface at a level below an activation current level when the master input voltage is applied to the high voltage switch by:
- asserting an enable pull-up (EN_PU) signal to activate a pull-up device;
- and
- providing, by the pull-up device, a low impedance path for a gate node of the high voltage switch to maintain the high voltage switch in an off state;
- and
- directly supplying, using the high voltage switch, the master input voltage to the high voltage power rail of the IO interface to maintain the power up sequence of the IO interface.
5 more elements
Dependencies are inferred from the claim text.