ESD protection circuit and method therefor

An electrostatic discharge (ESD) protection circuit comprising:

• a clamp circuit coupled between a first voltage supply node and a second voltage supply node, the clamp circuit including:
• a first transistor having a first current electrode, a second current electrode coupled at the second voltage supply node, and a control electrode coupled to the second voltage supply node by way of a first resistor;
• a second transistor coupled in series with the first transistor, the second transistor having a first current electrode coupled at the first voltage supply node, a second current electrode, and a control electrode coupled to the second current electrode of the second transistor by way of a second resistor;
• a first bias generator circuit coupled at the control electrode of the second transistor, the first bias generator circuit configured to cause a gate-to-source voltage of the second transistor to be substantially equal to a gate-to-source voltage of the first transistor during a normal operating mode;
• and
• a trigger circuit coupled with the clamp circuit, the trigger circuit having a first output coupled at the control electrode of the first transistor and a second output coupled at the control electrode of the second transistor, the trigger circuit configured to turn on the first transistor and the second transistor of the clamp circuit during an ESD event.

An electrostatic discharge (ESD) protection circuit comprising:

• a clamp circuit coupled between a first voltage supply node and a second voltage supply node, the clamp circuit including:
• a first transistor having a first current electrode, a second current electrode coupled at the second voltage supply node, a control electrode coupled to the second voltage supply node by way of a first resistor, and a body electrode coupled at the second voltage supply node;
• a second transistor having a first current electrode, a second current electrode coupled at the first current electrode of the first transistor at a first clamp node, a control electrode, and a body electrode coupled at the second current electrode;
• a third transistor having a first current electrode coupled at the first voltage supply node, a second current electrode coupled at the first current electrode of the second transistor at a second clamp node, a control electrode, and a body electrode coupled at the second current electrode;
• a first bias generator circuit coupled at the control electrode of the second transistor;
• a second bias generator circuit coupled at the control electrode of the third transistor;
• and
• a trigger circuit coupled with the clamp circuit, the trigger circuit having a first output coupled at the control electrode of the first transistor, a second output coupled at the control electrode of the second transistor, and a third output coupled at the control electrode of the third transistor.