Memory mirror sequencing for reduced latency in memory patching

An apparatus comprising:

• means for initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters;
• means for triggering a parallel and simultaneous ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters and a plurality of parallel and simultaneous ROM to RAM copy operations through a finite state machine (FSM);
• and
• means for executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern.

A method comprising:

• initializing a memory mirror sequence (MMS) controller for a plurality of parallel read only memory (ROM) to random access memory (RAM) copy operations for a random access memory (RAM) wherein the MMS controller includes one or more parallelization parameters;
• triggering a parallel and simultaneous ROM to RAM copy procedure using the MMS controller with the one or more parallelization parameters and a plurality of parallel and simultaneous ROM to RAM copy operations through a finite state machine (FSM);
• and
• executing a memory patching process to update one or more selected contents of the RAM for an updated built-in self-test (BIST) test pattern.