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US 12,770,703 B2Granted
Memory device and operating method thereof
AssigneesTaiwan Semiconductor Manufacturing Company, Ltd., National Tsing Hua University
InventorsWin-San Khwa, De-Qi You, Jui-Jen Wu, Meng-Fan Chang
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory array storing weights; a pre-charging circuit coupled to the memory array through data lines and charging, in response to a pre-charge signal, at least one data line in the data lines to a read voltage in a read operation to one in the weights; and a calibration circuit generating the pre-charge signal according to an address of the one in the weights.
Claims20
A memory device, comprising:
- a memory array configured to store a plurality of weights;
- a pre-charging circuit coupled to the memory array through a plurality of data lines, and configured to charge, in response to a pre-charge signal, at least one data line in the plurality of data lines to a read voltage in a read operation to one in the plurality of weights;
- and
- a calibration circuit configured to generate the pre-charge signal having a first pulse width according to an address of a first weight in the plurality of weights or generate the pre-charge signal having a second pulse width according to an address of a second weight in the plurality of weights,
- wherein the first pulse width and the second pulse width are different from each other.
2 more elements
A memory device, comprising:
- a memory array configured to store a plurality of weights;
- a pre-charging circuit coupled to the memory array through a plurality of data lines, and configured to:
- charge, in response to a pre-charge signal, the data line in the plurality of data lines to a first read voltage for a first duration in a read operation to a first weight in the plurality of weights;
- and
- charge, in response to the pre-charge signal, the data line in the plurality of data lines to a second read voltage for a second duration in the read operation to a second weight in the plurality of weights,
- wherein the first duration is different from the second duration;
- and
- a calibration circuit configured to generate the pre-charge signal according to an address of one of the first and second weights in the plurality of weights.
5 more elements
A memory device, comprising:
- a memory array configured to store a plurality of weights;
- a pre-charging circuit coupled to the memory array through a plurality of data lines, and configured to charge, in response to a pre-charge signal, at least one data line in the plurality of data lines to a read voltage in a read operation to one in the plurality of weights;
- and
- a calibration circuit configured to generate the pre-charge signal having a first pulse width according to an address of a first weight in the plurality of weights or generate the pre-charge signal having a second pulse width according to an address of a second weight in the plurality of weights,
- wherein the first pulse width and the second pulse width are different from each other,
- wherein the first weight is stored in a first portion of the memory array, and the second weight is stored in a second portion, different from the first portion, of the memory array.
3 more elements
Dependencies are inferred from the claim text.