Non-volatile memory with smart tail detection read mode without erase time penalty

A method, comprising:

• applying a sequence of one or more erase pulses to a block of non-volatile memory cells having a NAND architecture;
• maintaining an erase loop count of a number of the erase pluses of the sequence that have been applied to the block;
• subsequent to applying each of the erase pulses, performing an erase verify on the block;
• in response to the block not passing the erase verify, determining whether the erase loop count equals a first count value;
• in response to the erase loop count not equaling the first count value, incrementing the erase loop count and, for incremented erase loop counts less than a maximum value, applying the subsequent erase pulse of the sequence to the block;
• and
• in response to the erase loop count equaling the first count value, performing a tail detection read, the block including a plurality of NAND strings, each NAND string comprising a plurality of the memory cells connected in series between a corresponding bit line through one or more drain select gates and a source line though one or more source select gates, the tail detection read including:
• performing a read on a first of the select gates of each of the NAND strings of the block;
• determining whether more than a first number of the first select gates have threshold voltages above a first voltage level;
• in response to more than the first number of the first select gates having threshold voltages above the first voltage level, marking the block as defective and discontinuing the sequence of erase pulses;
• and
• in response to less than the first number of the first select gates having threshold voltages above the first voltage level, incrementing the erase loop count and, for incremented erase loop counts less than a maximum value, applying the subsequent erase pulse of the sequence to the block.

A non-volatile memory device, comprising:

• an array of non-volatile memory cells comprising a plurality of blocks, each block including a plurality of NAND strings, each NAND string comprising a plurality of the memory cells connected in series between a corresponding bit line through one or more drain select gates and a source line though one or more source select gates;
• and
• one or more control circuits configured to connect to the array and configured to:
• apply a sequence of one or more erase pulses to a block of non-volatile memory cells having a NAND architecture;
• maintain an erase loop count of a number of the erase pluses of the sequence that have been applied to the block;
• subsequent to applying each of the erase pulses, perform an erase verify on the block;
• in response to the block not passing the erase verify, determine whether the erase loop count equals a first count value;
• in response to the erase loop count not equaling the first count value, increment the erase loop count and, for incremented erase loop counts less than a maximum value, apply the subsequent erase pulse of the sequence to the block;
• and
• in response to the erase loop count equaling the first count value, perform a tail detection read, where, to perform the tail detection read, the one or more control circuits are configured to:
• perform a read on a first of the select gates of each of the NAND strings of the block;
• determine whether more than a first number of the first select gates have threshold voltages above a first voltage level;
• in response to more than the first number of the first select gates having threshold voltages above the first voltage level, mark the block as defective and discontinue the sequence of erase pulses;
• and
• in response to less than the first number of the first select gates having threshold voltages above the first voltage level, increment the erase loop count and, for incremented erase loop counts less than a maximum value, apply the subsequent erase pulse of the sequence to the block.