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AssigneeKioxia Corporation
InventorsViktoria Diana Schlykow, Reika Tanaka
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A semiconductor memory device of embodiments includes a semiconductor layer, a gate electrode layer, memory cells each including a gate insulating layer containing Si, O, and N, and a control circuit. The control circuit performs a write operation and an erase operation on the memory cells. The control circuit determine whether or not the number of times of execution of the erase operation on the memory cells has reached a predetermined number of times. When the number has reached the predetermined number of times, the control circuit perform first processing and second processing on the memory cells. The first processing applies a voltage with the same polarity as that in the write operation to the gate electrode layer with a pulse width larger than that in the write operation. The second processing applies a voltage with a polarity opposite to that in the write operation to the gate electrode layer.
A semiconductor memory device, comprising:
A semiconductor memory device, comprising:
A method for controlling a semiconductor memory device including a memory cell array including a first semiconductor layer extending in a first direction, a plurality of gate electrode layers stacked in the first direction, a first wiring electrically connected to one end of the first semiconductor layer, a second wiring electrically connected to the other end of the first semiconductor layer, and a plurality of first memory cells, each of the plurality of first memory cells including a part of the first semiconductor layer, one of the plurality of gate electrode layers, and a gate insulating layer including a first insulating region containing silicon (Si), oxygen (O), and nitrogen (N) and provided between the part of the first semiconductor layer and the one of the plurality of gate electrode layers, the method comprising:
Dependencies are inferred from the claim text.