Back to results
US 12,770,672 B2Granted
Low power clock injection during idle mode operations
AssigneeMicron Technology, Inc.
InventorsNoriaki Mochida, Takayuki Miyamoto, Kallol Mazumder, Scott E. Smith
Life of this patent
Estimating the term…
Abstract
An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.
Claims25
An apparatus, comprising:
- a synchronizer configured to receive an enable signal, a first clock signal, and a signal to enter a low power mode and to provide an output signal, wherein in response to the signal to enter the low power mode the synchronizer is configured to intermittently enable and disable the output signal based on the enable signal;
- and
- a clock driver circuit configured to receive the first clock signal and intermittently enable and disable a second clock signal based on the output signal.
A memory, comprising:
- an input/output circuit coupled to data terminals;
- a command decoder configured to receive a power saving mode register setting (MRS) command via a command bus and to responsively provide a low power mode command signal;
- a synchronizer configured to receive the low power mode command signal, an enable signal, and a first clock signal and to provide an output signal, wherein the synchronizer is configured to intermittently enable and disable the output signal based on the enable signal;
- and
- a clock driver circuit configured to receive the first clock signal and intermittently enable and disable provision of a second clock signal to the input/output circuit based on the output signal.
2 more elements
A method, comprising:
- generating an enable signal based on negative-bias temperature instability (NBTI) of a circuit component of a memory;
- and
- in response to a mode register setting (MRS) command to enter a power savings mode, intermittently enabling and disabling a clock signal based on the enable signal.
Dependencies are inferred from the claim text.