Complementary ferroelectric logic

A device, comprising:

• an upper ferroelectric tunnel junction (FTJ) device adapted to be in one of a high or a low resistance state, to receive a write pulse, and to receive a subsequent read pulse;
• and
• a lower FTJ device electrically connected to the upper FTJ device at an intervening node, the lower FTJ device adapted to be in one of the high or the low resistance state;
• wherein:
• the write pulse is adapted to place each of the upper and lower FTJ devices in a corresponding one of the high or the low resistance state;
• the subsequent read pulse is adapted to cause the device to output, at the intervening node, an output pulse indicative of a logic state of the device;
• and
• the device implements an inverter circuit.

A device, comprising:

• an upper ferroelectric tunnel junction (FTJ) device adapted to be in one of a high or a low resistance state, to receive a write pulse, and to receive a subsequent read pulse;
• and
• a lower FTJ device electrically connected to the upper FTJ device at an intervening node, the lower FTJ device adapted to be in one of the high or the low resistance state;
• wherein:
• the write pulse is adapted to place each of the upper and lower FTJ devices in a corresponding one of the high or the low resistance state;
• the subsequent read pulse is adapted to cause the device to output, at the intervening node, an output pulse indicative of a logic state of the device;
• and
• the device implements a NAND circuit;
• and
• the device further comprises a second upper FTJ device in parallel with the upper FTJ device, the second upper FTJ device electrically connected to the intervening node, the second upper FTJ device adapted to be in one of the high or the low resistance state, the second upper FTJ adapted to receive a second write pulse, and the second write pulse adapted to place each of the second upper and lower FTJ devices in a corresponding one of the high or the low resistance state.