Method for efficiently waking up ferroelectric memory

A method for waking up ferroelectric memory, comprising steps of:

• forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cell includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode;
• and
• applying a voltage signal to the ferroelectric memory cell to rise a percentage of molecules of a ferroelectric phase in the ferroelectric structure to a range from 50% to 100%,
• wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts, and
• wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion.

A method for waking up ferroelectric memory, comprising steps of:

• forming a ferroelectric memory cell on a semiconductor substrate, wherein the ferroelectric memory cell includes a ferroelectric capacitor that has a first capacitor electrode, a second capacitor electrode and a ferroelectric structure disposed between the first capacitor electrode and the second capacitor electrode;
• and
• applying a voltage signal to the ferroelectric memory cell to increase each of a positive remnant polarization value and a negative remnant polarization value of the ferroelectric structure in magnitude,
• wherein the voltage signal is applied in such a way that a wake-up voltage signal across the ferroelectric capacitor has a positive voltage portion and a negative voltage portion that are asymmetric with respect to zero volts, and
• wherein the asymmetry between the positive voltage portion and the negative voltage portion is configured based on a difference between work functions of the first capacitor electrode and the second capacitor electrode in such a way that the difference between work functions of the first capacitor electrode and the second capacitor electrode is compensated for by the asymmetry between the positive voltage portion and the negative voltage portion.