Semiconductor memory apparatus and an operating method of the semiconductor memory apparatus

An operating method of a semiconductor memory apparatus, the method comprising:

• electrically isolating a bitline from a first input node of a bitline sense amplifier, and electrically isolating a bitline bar from a second input node of the bitline sense amplifier;
• performing a mismatch compensation operation with the bitline sense amplifier, and enabling a wordline to electrically couple a memory cell to the bitline during performing the mismatch compensation operation;
• electrically coupling the first input node with the bitline, and electrically coupling the second input node with the bitline bar;
• and
• developing a voltage level difference of a first node and a second node by amplifying voltage levels of the first and second input nodes.

A semiconductor memory apparatus comprising:

• a sub-wordline driver configured to receive a wordline control signal and enable one of a first wordline coupled with a first bitline and a second wordline coupled with a second bitline based on the wordline control signal, and configured to delay the wordline control signal to generate one of a first bitline switching signal and a second bitline switching signal;
• a bitline sense amplifier configured to amplify and latch voltage levels of a global bitline and a global bitline bar;
• and
• a bitline switching circuit configured to electrically couple the first bitline and a first bitline bar with the global bitline and the global bitline bar, respectively, in response to the first bitline switching signal, and configured to electrically couple the second bitline and a second bitline bar with the global bitline and the global bitline bar, respectively, in response to the second bitline switching signal.

An operating method of a semiconductor memory apparatus, the method comprising:

• electrically isolating first and second bitlines from a global bitline and electrically isolating first and second bitline bars from a global bitline bar;
• performing a mismatch compensation operation with a bitline sense amplifier;
• enabling one of first and second wordlines to electrically couple one of the first and second bitlines to a memory cell;
• electrically coupling a bitline electrically coupled with an enabled wordline between the first and second bitlines with the global bitline;
• and
• developing a voltage level difference of a first node and a second node by amplifying voltage levels of the global bitline and the global bitline bar.