Shift register, gate driving circuit and display panel

A gate driving circuit, comprising a plurality of shift registers cascaded in sequence, wherein the shift register comprises:

• a first input sub-circuit, configured to cause, in response to a first level of a first-type clock signal end, a signal of a first power supply voltage end to be written into a first node;
• a second input sub-circuit, configured to cause, in response to a first level on a signal input end, a signal of the first-type clock signal end to be written into the first node;
• a first output sub-circuit, comprising a first output unit, wherein the first output unit is configured to cause, in response to a first level on the first node, a signal of a second power supply voltage end to be written into a signal output end;
• a first control sub-circuit, configured to cause, in response to the first level on the signal input end, a signal of a second-type clock signal end to be written into a second node;
• a second control sub-circuit, configured to cause, in response to the first level on the first node, the signal of the second-type clock signal end to be written into a third node;
• a third control sub-circuit, configured to cause, in response to the first level of the first-type clock signal end, conduction between the third node and the second node;
• and
• a second output sub-circuit, comprising a second output unit, wherein the second output unit is configured to cause, in response to a first level on the second node, the signal of the first power supply voltage end to be written into the signal output end;
• in two adjacent stages of the shift registers, the signal output end of the shift register of a previous stage is electrically connected to the signal input end of the shift register of a next stage;
• in the gate driving circuit, the signal input end of the shift register of a first stage is electrically connected to a start signal end;
• the gate driving circuit comprises a plurality of shift register groups, wherein the shift register group comprises a first shift register, a second shift register and a third shift register cascaded in sequence;
• the first-type clock signal end of the first shift register is electrically connected to a third clock signal wiring, and the second-type clock signal end of the first shift register is electrically connected to a first clock signal wiring;
• the first-type clock signal end of the second shift register is electrically connected to the first clock signal wiring, and the second-type clock signal end of the second shift register is electrically connected to a second clock signal wiring;
• and
• the first-type clock signal end of the third shift register is electrically connected to the second clock signal wiring, and the second-type clock signal end of the third shift register is electrically connected to the third clock signal wiring.

A display panel, comprising a gate driving circuit, wherein the gate driving circuit comprises a plurality of shift registers cascaded in sequence, and the shift register comprises:

• a first input sub-circuit, configured to cause, in response to a first level of a first-type clock signal end, a signal of a first power supply voltage end to be written into a first node;
• a second input sub-circuit, configured to cause, in response to a first level on a signal input end, a signal of the first-type clock signal end to be written into the first node;
• a first output sub-circuit, comprising a first output unit, wherein the first output unit is configured to cause, in response to a first level on the first node, a signal of a second power supply voltage end to be written into a signal output end;
• a first control sub-circuit, configured to cause, in response to the first level on the signal input end, a signal of a second-type clock signal end to be written into a second node;
• a second control sub-circuit, configured to cause, in response to the first level on the first node, the signal of the second-type clock signal end to be written into a third node;
• a third control sub-circuit, configured to cause, in response to the first level of the first-type clock signal end, conduction between the third node and the second node;
• and
• a second output sub-circuit, comprising a second output unit, wherein the second output unit is configured to cause, in response to a first level on the second node, the signal of the first power supply voltage end to be written into the signal output end;
• in two adjacent stages of the shift registers, the signal output end of the shift register of a previous stage is electrically connected to the signal input end of the shift register of a next stage;
• in the gate driving circuit, the signal input end of the shift register of a first stage is electrically connected to a start signal end;
• the gate driving circuit comprises a plurality of shift register groups, wherein the shift register group comprises a first shift register, a second shift register and a third shift register cascaded in sequence;
• the first-type clock signal end of the first shift register is electrically connected to a third clock signal wiring, and the second-type clock signal end of the first shift register is electrically connected to a first clock signal wiring;
• the first-type clock signal end of the second shift register is electrically connected to the first clock signal wiring, and the second-type clock signal end of the second shift register is electrically connected to a second clock signal wiring;
• and
• the first-type clock signal end of the third shift register is electrically connected to the second clock signal wiring, and the second-type clock signal end of the third shift register is electrically connected to the third clock signal wiring.