Scan driver

A scan driver comprising:

• stage groups each including a first scan stage and a second scan stage,
• wherein each of the first and second scan stages outputs a carry signal and a scan signal in response to a previous carry signal provided from a previous stage group,
• wherein each of the stage groups stores the previous carry signal provided from the previous stage group in a first capacitor,
• wherein each of the stage groups discharges a voltage stored in the first capacitor for the first and second scan stages to a second voltage level in response to a first control signal of a first control line, and
• wherein each of the stage groups includes:
• a fifth transistor including a first electrode electrically connected to a second control line, a second electrode electrically connected to a first node, and a gate electrode;
• the first capacitor electrically connected between the second control line and the gate electrode of the fifth transistor;
• and
• a third transistor including a first electrode electrically connected to a previous carry line, a second electrode electrically connected to the gate electrode of the fifth transistor, and a gate electrode electrically connected to the first control line, and
• wherein each of the first and second scan stages includes:
• a second transistor including a first electrode electrically connected to a corresponding previous carry line, a second electrode electrically connected to a Q node, and a gate electrode electrically connected to the first electrode of the second transistor;
• a ninth transistor including a first electrode electrically connected to a carry clock line, a second electrode electrically connected to a corresponding carry line, and a gate electrode electrically connected to the Q node;
• a first transistor including a first electrode electrically connected to a scan clock line, a second electrode electrically connected to a corresponding scan line, and a gate electrode electrically connected to the Q node;
• a sixth transistor including a first electrode electrically connected to the first node, a second electrode electrically connected to the Q node, and a gate electrode electrically connected to a third control line;
• a twenty-fifth transistor including a first electrode electrically connected to a fifth control line, a second electrode, and a gate electrode electrically connected to the fifth control line;
• and
• a twenty-sixth transistor including a first electrode electrically connected to the fifth control line, a second electrode electrically connected to a QB node, and a gate electrode electrically connected to the second electrode of the twenty-fifth transistor.