Logic cell placement mechanisms for improved clock on-chip variation
AssigneeNVIDIA Corporation
InventorsAnand Kumar Rajaram, Erik Welty, David Lyndell Brown
Life of this patent
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Abstract
Mechanisms to place flip-flops and other synchronous logic cells in a circuit layout in a clock on-chip variation-aware, predetermined order based on analysis of the clock gating, connectivity, and logic depth of the unplaced netlist. The resulting placements enable clock trees having a regular structure leading to improvements in clock on-chip variation, timing, and clock power.
Claims20
A method of generating a clock tree for a circuit, the method comprising:
- clustering synchronous logic cells of the circuit according to their interactive timing behavior;
- placing resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches;
- and
- generating the clock tree as traces from centers of the patches to the cells.
A non-transitory computer-readable storage medium, the computer-readable storage medium including instructions that when executed by a computer, cause the computer to:
- cluster synchronous logic cells of a circuit according to their interactive timing behavior;
- place resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches, the placement of the resulting clusters made with higher priority over placement of asynchronous logic cells of the circuit;
- and
- generate a right-angled clock tree between the cells and between the patches.
A computing apparatus comprising:
- at least one processor;
- and
- a memory storing instructions that, when executed by the processor, configure the apparatus to:
- cluster synchronous logic cells of the circuit;
- place resulting clusters of the synchronous logic cells in the circuit in cells of diamond-shaped patches, the cells generated by repeatedly sub-dividing the diamond shaped patches into smaller cells;
- and
- generate portions of a clock tree within the patches.
Dependencies are inferred from the claim text.