Modeling mandrel tolerance in a design of a semiconductor device

A system for improving a design of a semiconductor device, the system comprising:

• a processor;
• and
• a memory storing instructions, which when executed by the processor, cause the processor to perform operations comprising:
• accessing design parameters of a plurality of transistors that form at least part of the semiconductor device, the design parameters comprising a plurality of fins associated with each of the plurality of transistors;
• generating a fin index identifying each of the plurality of fins;
• grouping the fin indexes of the plurality of fins into two or more groups based on respective fin types of the plurality of fins, wherein the respective fin types are determined based on a first spacing between each fin and an adjacent fin on one side of each fin and a second spacing between each fin and an adjacent fin on another side of each fin;
• responsive to determining that a first fin index associated with a first transistor of the plurality of transistors belongs to a group that is different from a second fin index associated with a second transistor of the plurality of transistors, identifying a mandrel mismatch;
• and
• determining a device parameter based on the identified mandrel mismatch.

A non-transitory computer-readable medium storing instructions executable by a processor, causing the processor to perform operations comprising:

• accessing design parameters of a plurality of transistors that form at least part of a semiconductor device, the design parameters comprising a plurality of fins associated with each of the plurality of transistors;
• generating a fin index identifying each of the plurality of fins;
• grouping the fin indexes of the plurality of fins into two or more groups based on respective fin types of the plurality of fins, wherein the respective fin types are determined based on a first spacing between each fin and an adjacent fin on one side of each fin and a second spacing between each fin and an adjacent fin on another side of each fin;
• responsive to determining that a first fin index associated with a first transistor of the plurality of transistors belongs to a group that is different from a second fin index associated with a second transistor of the plurality of transistors, identifying a masking layer mismatch;
• and
• determining a device parameter based on the identified masking layer mismatch.