Systems and methods for implementing design of semiconductor packages

A method for verifying a semiconductor package, comprising:

• receiving a behavioral description of each of a plurality of logic chips;
• generating first netlists based on the behavioral descriptions of the logic chips;
• receiving connection information of a plurality of non-logic structures, wherein the connection information comprises overall physical arrangement and connectivity among the plurality of logic chips and the plurality of non-logic structures;
• generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces operatively corresponds to an interface between a pair of one of the logic chips and one of the non-logic structures;
• generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges, wherein the first vertices correspond to the logic chips, respectively, the second vertices correspond to the non-logic structures, respectively, and the third vertices correspond to the virtual interfaces, respectively;
• and
• transforming the first netlists to a second netlist based on the graph.

A computer program product comprising a computer-readable program medium code stored thereupon, the code, when executed by a processor, causing the processor to implement a method, comprising:

• receiving a behavioral description of each of a plurality of logic chips;
• generating first netlists based on the behavioral descriptions of the logic chips;
• receiving connection information of a plurality of non-logic structures, wherein the connection information comprises overall physical arrangement and connectivity among the plurality of logic chips and the plurality of non-logic structures;
• generating a plurality of virtual interfaces, wherein each of the plurality of virtual interfaces operatively corresponds to an interface between a pair of one of the logic chips and one of the non-logic structures;
• generating a graph consisting of a plurality of first vertices, a plurality of second vertices, a plurality of third vertices, and a plurality of edges, wherein the first vertices correspond to the logic chips, respectively, the second vertices correspond to the non-logic structures, respectively, and the third vertices correspond to the virtual interfaces, respectively;
• and
• transforming the first netlists to a second netlist based on the graph.