Auto compaction tool for electronic design automation
AssigneeD2S, Inc.
InventorsDonald Oriordan, Akira Fujimura, George Janac
Life of this patent
Estimating the term…
Abstract
A method for manufacturing-aware editing of circuit layouts driven by predictions regarding predicted manufactured wafer contours generated by a machine-trained network. The method allows for fast edit loops in interactive editing timeframes, in which the predicted manufactured wafer contours corresponding to design edits are presented within seconds of the edits themselves. In some embodiments, the wafer contours take mask OPC/ILT and lithography effects into account, as determined by the machine trained network.
Claims16
A method for compacting an integrated circuit (IC) design layout comprising a plurality of components, the method comprising
- for the design layout, iteratively:
- performing a compaction operation to compact the design layout;
- producing expected manufactured shapes of a set of routes in the compacted design layout;
- and
- using the expected manufactured shapes to assess whether another compaction operation should be performed,
- wherein producing the expected manufactured shapes comprises using a machine-trained network to produce a multi-contour display for each of a plurality of routes, each particular multi-contour display of each particular route in the plurality of routes representing a range of expected manufactured shapes for the particular route and having a plurality of contours corresponding to a plurality of variations of a parameter associated with a manufacturing process that is used to produce an IC from the IC design layout.
A non-transitory machine readable medium storing a program that when executed by one or more processing units of a computer compacts an integrated circuit (IC) design layout, the design layout comprising a plurality of components, the program comprising sets of instructions for:
- iteratively:
- performing a compaction operation to compact the design layout;
- producing expected manufactured shapes of a set of routes in the compacted design layout by using a machine-trained network to produce a multi-contour display for each of a plurality of routes, each particular multi-contour display of each particular route in the plurality of routes representing a range of expected manufactured shapes for the particular route and having a plurality of contours corresponding to a plurality of variations of a parameter associated with a manufacturing process that is used to produce an IC from the IC design layout;
- and
- using the expected manufactured shapes to assess whether another compaction operation should be performed.
Dependencies are inferred from the claim text.