Data processing device with register storing setting, security and communication information for read and write requests

A data processing device comprising:

• a register including, as address regions, a setting region that stores setting information transmitted from a host, a security data region that stores security data for the setting information, and a communication information region that stores communication information with the host
• a communication circuit that performs register communication between the host and the register;
• a communication counter including a writing counter that counts that a writing request for the setting information to the setting region has been made from the host, and a reading counter that counts that a reading request for the setting information has been made from the host;
• a sensor;
• a data output circuit that adds a counter value from the communication counter to sensor data outputted from the sensor and outputs the sensor data to the host, wherein the data output circuit adds the counter value from the communication counter to the sensor data, at a timing synchronized with a synchronization timing signal for the sensor data;
• and
• a notification circuit that outputs, as notification information, at least one of a processing status indicating a processing state in the register or error information caused in processing in the register,
• wherein the data output circuit adds the notification information from the notification circuit to the sensor data outputted from the sensor and outputs the sensor data to the host.

A data processing device comprising:

• a register including, as address regions, a setting region that stores setting information transmitted from a host, a security data region that stores security data for the setting information, and a communication information region that stores communication information with the host;
• a communication circuit that performs register communication between the host and the register;
• a communication counter including a writing counter that counts that a writing request for the setting information to the setting region has been made from the host, and a reading counter that counts that a reading request for the setting information has been made from the host;
• a sensor;
• a data output circuit that adds a counter value from the communication counter to sensor data outputted from the sensor and outputs the sensor data to the host, wherein
• the data output circuit adds the counter value from the communication counter to the sensor data, at a timing synchronized with a synchronization timing signal for the sensor data, the setting information transmitted from the host includes a counter expected value for a counter value of the writing counter, and the register includes an expected value register that stores the counter expected value;
• a memory that temporarily stores the setting information transmitted from the host;
• and
• a writing determination circuit that performs correctness determination of the setting information stored in the memory, on a basis of the security data, and reflects writing of the setting information in the setting region in a case where the setting information is determined as being correct and where the counter value of the writing counter and the counter expected value stored in the expected value register match.

A data processing device comprising:

• a register including, as address regions, a setting region that stores setting information transmitted from a host, a security data region that stores security data for the setting information, and a communication information region that stores communication information with the host;
• a communication circuit that performs register communication between the host and the register;
• a communication counter including a writing counter that counts that a writing request for the setting information to the setting region has been made from the host, and a reading counter that counts that a reading request for the setting information has been made from the host;
• a sensor;
• a data output circuit that adds a counter value from the communication counter to sensor data outputted from the sensor and outputs the sensor data to the host, wherein the data output circuit adds the counter value from the communication counter to the sensor data, at a timing synchronized with a synchronization timing signal for the sensor data;
• and
• a notification circuit that outputs, as notification information, at least one of a processing status indicating a processing state in the register or error information caused in processing in the register, wherein
• the notification circuit outputs the error information as the notification information, in a case where correctness determination of the setting information is performed on a basis of the security data and the setting information is determined as being incorrect.

A data processing device comprising:

• a register including, as address regions, a setting region that stores setting information transmitted from a host, a security data region that stores security data for the setting information, and a communication information region that stores communication information with the host;
• a communication circuit that performs register communication between the host and the register;
• a communication counter including a writing counter that counts that a writing request for the setting information to the setting region has been made from the host, and a reading counter that counts that a reading request for the setting information has been made from the host;
• a sensor;
• a data output circuit that adds a counter value from the communication counter to sensor data outputted from the sensor and outputs the sensor data to the host, wherein the data output circuit adds the counter value from the communication counter to the sensor data, at a timing synchronized with a synchronization timing signal for the sensor data, the setting information transmitted from the host includes a counter expected value for a counter value of the writing counter, and the register includes an expected value register that stores the counter expected value;
• and
• a notification circuit that outputs error information as notification information, in a case where the counter value of the writing counter and the counter expected value stored in the expected value register do not match.