Implementing asymmetric processor cores to enable higher operating frequencies in processor-based devices

A method for implementing asymmetric processor cores in processor-based devices, comprising:

• determining, by a dynamic voltage and frequency scaling (DVFS) circuit of a core cluster while only one or more processor cores of a first subset of processor cores of a plurality of processor cores of the core cluster are active, that one or more processor cores of a second subset of processor cores of the plurality of processor cores have become active, wherein:
• the core cluster comprises a phase-locked loop (PLL);
• the plurality of processor cores are based on a common instruction set architecture (ISA);
• each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL;
• each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores;
• and
• the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores;
• and
• responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switching, by the DVFS circuit, the core cluster from a first DVFS state to a second DVFS state lower than the first DVFS state.

A non-transitory computer-readable medium, having stored thereon computer-executable instructions that, when executed, cause a processor device of a processor-based device to:

• determine, while only one or more processor cores of a first subset of processor cores of a plurality of processor cores of a core cluster are active, that one or more processor cores of a second subset of processor cores of the plurality of processor cores have become active, wherein:
• the core cluster comprises a phase-locked loop (PLL);
• the plurality of processor cores are based on a common instruction set architecture (ISA);
• each processor core of the plurality of processor cores is configured to operate synchronously based on a same clock signal from the PLL;
• each processor core of the first subset of processor cores is implemented with a different physical characteristic relative to the second subset of processor cores;
• and
• the different physical characteristic enables a higher operating frequency of each processor core of the first subset of processor cores that that of each processor core of the second subset of processor cores;
• and
• responsive to determining that the one or more processor cores of the second subset of processor cores have become active, switch the core cluster from a first dynamic voltage and frequency scaling (DVFS) state to a second DVFS state lower than the first DVFS state.