Low latency gigabit PHY-based signal switching for emulation, prototyping, and high performance computing

A system, comprising:

• multiple integrated circuit (IC) devices configured as a mesh network, wherein a first one of the ICs devices comprises a field-programmable gate array (FPGA) configured to interface with FPGAs of other ones of the ICs devices via-point-to-point connections and to interface between second and third ones of the other ICs devices, and wherein the first IC comprises:
• a receiver comprising receive-side physical layer circuitry configured to de-serialize and extract data from a signal received from the second integrated circuit device;
• receive-side media access control circuitry configured to verify frame check sequences of the extracted data and provide processed data functional circuitry configured to receive the processed data;
• a transmitter comprising transmit-side media access control circuitry configured to frame outgoing data, and transmit-side physical layer circuitry configured to serialize and transmit the framed outgoing data;
• and
• a bypass circuit configured to bypass the functional circuitry and provide an output of one of the receive-side physical layer circuitry and the receive-side media access control circuitry to an input of a respective one of the transmit-side physical layer circuitry and the transmit-side media access control circuitry, in a bypass mode.

A method, comprising:

• interfacing with integrated circuit devices of a mesh network, by a first integrated circuit device that comprises a field-programmable gate arrays (FPGA), with other integrated circuit devices of a mesh network that comprise respective FPGAs, via point-to-point connections;
• and
• interfacing between second and third ones of the other integrated circuit devices, by the first integrated circuit device, comprising
• de-serializing and extracting data from a signal received from the second integrated circuit device, by receive-side physical layer circuitry of the first integrated circuit device;
• verifying frame check sequences of the extracted data and providing processed data, by receive-side media access control circuitry of the first integrated circuit device;
• and
• routing an output of one of the receive-side physical layer circuitry and the receive-side media access control circuitry to an input of a respective one of transmit-side physical layer circuitry and transmit-side media access control circuitry of the first integrated circuit device, bypassing functional circuitry of the first integrated circuit device, in a bypass mode.

A system, comprising:

• a first integrated circuit (IC) device configured to interface with other IC devices of a mesh network via point-to-point connections, including to interface between second and third ones of the other integrated circuit devices, wherein the first integrated circuit device comprises:
• a first transceiver configured to interface with the second IC device, comprising a first loopback path between a receiver and a transmitter of the first transceiver;
• and
• a second transceiver configured to interface with the third IC device, comprising a second loopback path between a receiver and a transmitter of the second transceiver;
• and
• a bypass link configured to provide data received from the second IC device, from the receiver of the first transceiver to the transmitter of the second transceiver for transmission to the third IC device, in a bypass mode.