Memory architecture

A method, comprising:

• configuring, according to a first latency of a memory device, a stream processor of a first processor, the stream processor configured to read from or write to the memory device at the first latency;
• configuring, according to a second latency of a second processor, a scheduling processor of the first processor, the scheduling processor configured to read from or write to one or more memory registers of the second processor at the second latency;
• providing data between the first processor and the memory device at the first latency;
• and
• providing data between the second processor and the stream processor at the second latency.

A system-on-a-chip (SoC), comprising:

• at least one graphics processing unit (GPU) providing multi-core parallel processing via a plurality of respective lanes, the GPU to:
• configure a first processor to read from or write to a memory device at a first latency of the memory device;
• configure the first processor to read from or write to one or more memory registers of a second processor at a second latency of the second processor;
• provide data between the first processor and the memory device at the first latency;
• and
• provide data between the second processor and the first processor at the second latency.