US 12,769,667 B1 · Translation invalidation filtering based on a context table within a processor core

Abstract

Implementations described herein relate to filtering translation invalidation messages within a core of a processor based on a context table. A core may include an address translation cache and a context table storing contexts in which the core has operated. A translation invalidation controller within the core may identify a context from a received translation invalidation message. Based on the context and the context table, the controller may determine if the address translation cache lacks entries targeted by the message. If so, the message may be discharged without accessing the address translation cache. This can reduce latency and processing overhead by avoiding unnecessary scans of the address translation cache for irrelevant messages. Corresponding processors and cores are also disclosed.

Claims20

Dependent claims

A method comprising:

identifying a context to which a message corresponds, the message being a translation invalidation message received by a first core of a processor from a second core of the processor;
determining, based on the context to which the message corresponds and a context table configured to store contexts in which the first core has operated, that an address translation cache of the first core lacks any entry targeted by the message;
and
based on the determining that the address translation cache lacks any entry targeted by the message, discharging the message without accessing the address translation cache.

1 more element

A first core of a processor, the first core comprising:

an address translation cache;
a context table configured to store contexts in which the first core has operated;
and
a translation invalidation controller configured to:
identify a context to which a message corresponds, the message being a translation invalidation message received by the first core from a second core of the processor;
determine, based on the context to which the message corresponds and the context table, that the address translation cache lacks any entry targeted by the message;
and
based on the determining that the address translation cache lacks any entry targeted by the message, discharge the message without accessing the address translation cache.

5 more elements

A processor comprising:

a first core including an address translation cache and a context table configured to store contexts in which the first core has operated;
and
a second core configured to dispatch a message to the first core, the message being a translation invalidation message;
wherein, upon receiving the message from the second core, the first core is configured to:
identify a context to which the message corresponds,
determine, based on the context to which the message corresponds and the context table, that the address translation cache lacks any entry targeted by the message, and
based on the determining that the address translation cache lacks any entry targeted by the message, discharge the message without accessing the address translation cache.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/225,679Filed 2 Jun 2025

Granted

20 Oct 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification5 codes

G06F 12/0891
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 9/30043
To perform operations on memory: lOAD or STORE instructions; Clear instruction
G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache

Translation invalidation filtering based on a context table within a processor core

Life of this patent

Translation invalidation filtering based on a context table within a processor core

Life of this patent

Abstract

Claims20