Limited write completion return for rate control in a memory sub-system with single-level cell memory caching
AssigneeMicron Technology, Inc.
InventorsPaul Roger Stonelake, Ramkumar Venkatachalam
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Abstract
Processing logic in a memory sub-system receives, from a host system, a plurality of write commands for writing data to the memory device. Upon writing the data to a cache of the memory device, the processing logic generates a plurality of completion entries, the plurality of completion entries corresponding to the plurality of write commands and comprising respective timestamps, wherein the respective timestamps are based on a target host-to-cache data rate, and sends the plurality of completion entries to the host system based on the respective timestamps.
Claims20
A system comprising:
- a memory device;
- and
- a processing device, operatively coupled with the memory device, to perform operations comprising:
- receiving, from a host system, a plurality of write commands for writing data to the memory device;
- upon writing the data to a cache of the memory device, generating a plurality of completion entries, the plurality of completion entries corresponding to the plurality of write commands and comprising respective timestamps, wherein the respective timestamps are calculated for the plurality of write commands based on an amount of available storage space in the cache and a target rate for migrating data from the cache to a primary storage band of the memory device, and wherein each respective timestamp represents a future time when a corresponding completion entry is to be sent to the host system to achieve a target host-to-cache data rate;
- and
- sending the plurality of completion entries to the host system based on the respective timestamps.
A method comprising:
- receiving, from a host system, a plurality of write commands for writing data to a memory device;
- upon writing the data to a cache of the memory device, generating a plurality of completion entries, the plurality of completion entries corresponding to the plurality of write commands and comprising respective timestamps, wherein the respective timestamps are calculated for the plurality of write commands based on an amount of available storage space in the cache and a target rate for migrating data from the cache to a primary storage band of the memory device, and wherein each respective timestamp represents a future time when a corresponding completion entry is to be sent to the host system to achieve a target host-to-cache data rate;
- and
- sending the plurality of completion entries to the host system based on the respective timestamps.
A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:
- receiving, from a host system, a plurality of write commands for writing data to a memory device;
- upon writing the data to a cache of the memory device, generating a plurality of completion entries, the plurality of completion entries corresponding to the plurality of write commands and comprising respective timestamps, wherein the respective timestamps are calculated for the plurality of write commands based on an amount of available storage space in the cache and a target rate for migrating data from the cache to a primary storage band of the memory device, and wherein each respective timestamp represents a future time when a corresponding completion entry is to be sent to the host system to achieve a target host-to-cache data rate;
- and
- sending the plurality of completion entries to the host system based on the respective timestamps.
Dependencies are inferred from the claim text.