Decoding device and memory system

A decoding device configured to decode first data being input to the decoding device, the decoding device comprising:

• extraction circuitry configured to extract one or more symbols from the first data;
• and
• decoding circuitry configured to perform a decoding process on the one or more symbols,
• the extraction circuitry comprising:
• a first code length calculation circuit configured to calculate first code lengths of respective first symbols, assuming that bits of a first bit string are starting locations of the first symbols, respectively, and that the first symbols are encoded by a first encoding scheme, the bits of the first bit string being included in an extraction range of the first data;
• a second code length calculation circuit configured to calculate second code lengths of respective second symbols, assuming that the bits of the first bit string are starting locations of the second symbols and that the second symbols are encoded by a second encoding scheme;
• a first determination circuit configured to determine first context information indicating that each of third symbols is encoded by any one of the first encoding scheme and the second encoding scheme, the third symbols following the first symbols, respectively;
• a second determination circuit configured to determine second context information indicating that each of fourth symbols is encoded by any one of the first encoding scheme and the second encoding scheme, the fourth symbols following the second symbols, respectively;
• a first register configured to store the first context information, and first boundary location information that indicates an initial bit location of each of the third symbols and is determined based on the first code lengths;
• a second register configured to store the second context information, and second boundary location information that indicates an initial bit location of each of the fourth symbols and is determined based on the second code lengths;
• a first update circuit configured to:
• acquire third context information and third boundary location information that correspond to fifth symbols, based on the first context information and the first boundary location information that are stored in the first register, the fifth symbols following the third symbols, respectively, the third boundary location information indicating an initial bit of each of the fifth symbols;
• and
• store the third context information and the third boundary location information in the first register;
• and
• a second update circuit configured to:
• acquire fourth context information and fourth boundary location information that correspond to sixth symbols, based on the second context information and the second boundary location information that are stored in the second register, the sixth symbols following the fourth symbols, respectively, the fourth boundary location information indicating an initial bit of each of the sixth symbols;
• and
• store the fourth context information and the fourth boundary location information in the second register,
• the extraction circuitry further including an output circuit configured to:
• extract one or more symbols from a bit string in the extraction range, based on pieces of context information and pieces of boundary location information that are stored in the first register and the second register;
• and
• output the one or more extracted symbols to the decoding circuitry,
• the decoding circuitry being configured to perform the decoding process on each of the one or more extracted symbols.