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US 12,769,611 B2Granted
Controller, memory device and memory system
AssigneeSK hynix Inc.
InventorsJae Il Lim, Dong Hun Jeong, Jae Won Chung
Life of this patent
Estimating the term…
Abstract
When processing data corresponding to a command, a memory system processes the data by operating at least two banks included in a memory device. The operation of the banks according to the command is distributed, so the number of bits of data provided from a bank in which an error occurs is reduced, and the error may be corrected using a parity of a smaller number of bits.
Claims18
A memory system comprising:
- an N (where N is an integer satisfying N≥2) number of memory devices, each memory device including a first bank and a second bank that is paired with the first bank;
- and
- a controller configured to read M (where M is an integer satisfying M≥2) bits of first data from the first bank of each of the N number of memory devices, to read M bits of second data from the second bank of each of the N number of memory devices, and to process a codeword of 2·N·M bits, which is configured using the first data and the second data obtained from each of the N number of memory devices,
- wherein 2M bits of data is read from each of the N number of memory devices, and the first data and the second data are read from different banks included in each of the N number of memory devices.
1 more element
A controller comprising:
- a control circuit configured to output a first read command for a first bank included in each of an N (where N is an integer satisfying N≥2) number of memory devices and a second read command for a second bank included in each of the N number of memory devices, to pair the second bank and the first bank in each of the N number of memory devices, and to obtain M (where M is an integer satisfying M≥2) bits of first data corresponding to the first read command and M bits of second data corresponding to the second read command, wherein 2M bits of data is read from each of the N number of memory devices, and the first data and the second data are read from different banks included in each of the N number of memory devices;
- and
- an error correction circuit configured to correct an error in the first data obtained from the first bank included in one of the N number of memory devices or the second data obtained from the second bank included in one of the N number of memory devices, using a parity of K (where K is an integer satisfying K≥2) bits included in a codeword of 2·N·M bits, which is configured using the first data and the second data obtained from each of the N number of memory devices.
A memory device comprising:
- a first bank including a plurality of first word lines, a plurality of first bit lines and a plurality of first memory cells;
- and
- a second bank paired with the first bank, and including a plurality of second word lines, a plurality of second bit lines and a plurality of second memory cells,
- wherein M (where M is an integer satisfying M≥2) bits of first data read from the first bank and M bits of second data read from the second bank are provided in response to a single command, wherein 2M bits of data is provided in response to the single command, and the first data and the second data are read from different banks.
1 more element
Dependencies are inferred from the claim text.