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US 12,769,527 B2Granted
Method and apparatus for compiling for overlapping instructions on multiple processors
AssigneeMoreh Corp.
InventorsGangwon Jo, Jungho Park
Life of this patent
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Abstract
A method for compiling for overlapping instructions between a plurality of processors is provided, which is performed by one or more processors, and includes receiving a source program, determining a plurality of instructions to be executed in the plurality of processors based on the source program, and assigning the plurality of instructions to the plurality of processors such that a first portion of the plurality of instructions and a second portion of the plurality of instructions are processed in parallel by each of the plurality of processors.
Claims20
A method performed by one or more processors, the method comprising:
- receiving a source program;
- determining, based on the source program, a plurality of instructions to be executed in a plurality of processors;
- generating an intermediate representation graph corresponding to the plurality of instructions to be executed in the plurality of processors;
- based on the intermediate representation graph, identifying, in the plurality of instructions:
- a communication start-instruction associated with data transmission, and
- a wait instruction corresponding to waiting for the data transmission to end;
- rearranging the intermediate representation graph by inserting, after the communication start-instruction and before the wait instruction, one or more operation instructions such that a difference between a total execution time of the one or more operation instructions and a first execution time corresponding to the communication instruction and the wait instruction is less than a predetermined threshold time;
- and
- assigning, based on the rearranged intermediate representation graph, the plurality of instructions to the plurality of processors such that a first portion of the plurality of instructions and a second portion of the plurality of instructions are processed in parallel by at least two processors of the plurality of processors.
6 more elements
An apparatus comprising:
- one or more processors;
- and
- memory storing instructions that, when executed by the one or more processors, cause the apparatus to:
- receive a source program;
- determine, based on the source program, a plurality of instructions to be executed in a plurality of processors;
- generate an intermediate representation graph corresponding to the plurality of instructions to be executed in the plurality of processors;
- based on the intermediate representation graph, identify, in the plurality of instructions:
- a communication instruction associated with data transmission, and
- a wait instruction corresponding to waiting for the data transmission to end;
- rearrange the intermediate representation graph by inserting, after the communication instruction and before the wait instruction, one or more operation instructions such that a difference between a total execution time of the one or more operation instructions and a first execution time corresponding to the communication instruction and the wait instruction is less than a predetermined threshold time;
- and
- assign, based on the rearranged intermediate representation graph, the plurality of instructions to the plurality of processors such that a first portion of the plurality of instructions and a second portion of the plurality of instructions are processed in parallel by at least two processors of the plurality of processors.
9 more elements
One or more non-transitory computer-readable media storing instructions that, when executed, cause an apparatus to:
- receive a source program;
- determine, based on the source program, a plurality of instructions to be executed in a plurality of processors;
- generate an intermediate representation graph corresponding to the plurality of instructions to be executed in the plurality of processors;
- based on the intermediate representation graph, identify, in the plurality of instructions:
- a communication instruction associated with data transmission by, and
- a wait instruction corresponding to waiting for the data transmission to end;
- rearrange the intermediate representation graph by inserting, after the communication instruction and before the wait instruction, one or more operation instructions such that a difference between a total execution time of the one or more operation instructions and a first execution time corresponding to the communication instruction and the wait instruction is less than a predetermined threshold time;
- and
- assign, based on the rearranged intermediate representation graph, the plurality of instructions to the plurality of processors such that a first portion of the plurality of instructions and a second portion of the plurality of instructions are processed in parallel by at least two processors of the plurality of processors.
6 more elements
Dependencies are inferred from the claim text.