Memory device
AssigneeSK hynix Inc.
InventorsSu Jeong Oh, Sung Ho Bae, Je Bock Chung, Beom Seok Hah
Life of this patent
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Abstract
A memory device includes memory cells and a control unit. The memory cells are coupled in series between one or more first selection transistors coupled in series to a source line and one or more second selection transistors coupled in series to a bit line. The control unit is configured to apply, during a forcing period that is part of a rising period during which an increasing erase voltage is applied to the bit line, an increasing selection voltage to local selection lines coupled to the one or more first selection transistors and the one or more second selection transistors.
Claims19
A memory device comprising:
- memory cells coupled in series between one or more first selection transistors coupled in series to a source line and one or more second selection transistors coupled in series to a bit line;
- and
- a control unit including a voltage supply unit configured to output a selection voltage while increasing a voltage level of the selection voltage during a forcing period that is included in a rising period during which an erase voltage is applied to the bit line and increases;
- wherein the control unit is configured to apply, during the forcing period, the selection voltage output from the voltage supply unit to local selection lines coupled to the one or more first selection transistors and the one or more second selection transistors, and to float the local selection lines after an end of the forcing period.
A memory device comprising:
- memory cells coupled in series between one or more first selection transistors coupled in series to a source line and one or more second selection transistors coupled in series to a bit line;
- and
- a control unit including a connection unit coupled between global selection lines and local selection lines coupled to the one or more first selection transistors and the one or more second selection transistors;
- wherein an erase voltage applied to the bit line increases during a rising period including a forcing period;
- wherein the control unit is configured to, during the forcing period, apply voltages to the global selection lines such that voltage levels of the global selection lines increase;
- wherein the control unit is further configured to enable the connection unit during the forcing period such that voltages applied to the global selection lines are transferred to the local selection lines;
- and
- wherein the control unit is further configured to disable the connection unit at an end of the forcing period.
A memory device comprising:
- memory cells coupled in series between one or more first selection transistors coupled in series to a source line and one or more second selection transistors coupled in series to a bit line, the one or more first selection transistors and the one or more second selection transistors coupled to local selection lines;
- and
- a control unit including a voltage supply unit;
- wherein the control unit is configured to, during a rising period during which an erase voltage applied to the bit line increases, control an output level of the voltage supply unit and apply, to the local selection lines, a voltage output from the voltage supply unit such that voltage levels of the local selection lines increase to a target selection voltage;
- and
- wherein the control unit is further configured to float the local selection lines before an end of the rising period.
Dependencies are inferred from the claim text.