Memory access latency estimation method and memory access latency estimation system for estimating an access latency of a memory according to a plurality of coefficients and a plurality of indexes

A memory access latency estimation system, comprising:

• a first monitor configured to measure a first access latency of a first access operation of a first memory, wherein the first memory comprises a dynamic random-access memory;
• a plurality of second monitors configured to measure a plurality of first indexes of the first memory corresponding to the first access operation;
• and
• a hardware-implemented processor configured to use a plurality of first coefficients and the plurality of first indexes to perform a first weighted calculation to generate a first estimated latency, adjust the plurality of first coefficients to generate a plurality of updated first coefficients using a machine learning model implemented in hardware circuitry of the processor in order to use the plurality of updated first coefficients and the plurality of first indexes to perform the first weighted calculation to adjust the first estimated latency for the first estimated latency to approximate the first access latency, and use the plurality of updated first coefficients and a plurality of second indexes of the first memory to perform a second weighted calculation to generate a second estimated latency for a second access operation;
• wherein the processor comprises a member selected from a group comprising a central processing unit (CPU), a graphic processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), an application specific integrated circuit (ASIC), a deep learning processing unit (DPU), a vector processing unit (VPU), and a microprocessor, number and types of the plurality of first indexes are the same as number and types of the plurality of second indexes, the plurality of second indexes are corresponding to the second access operation, and the first access operation precedes the second access operation.

A memory access latency estimation method of a memory access latency estimation system, the memory access latency estimation system comprising a plurality of first monitors, a plurality of second monitors, and a processor, the processor being hardware-implemented, the processor comprising a member selected from a group comprising a central processing unit (CPU), a graphic processing unit (GPU), a tensor processing unit (TPU), a neural network processing unit (NPU), an application specific integrated circuit (ASIC), a deep learning processing unit (DPU), a vector processing unit (VPU), and a microprocessor, the memory access latency estimation method comprising:

• measuring, by the plurality of first monitors, a plurality of first indexes of a first dynamic random-access memory;
• measuring, by the plurality of second monitors, a plurality of second indexes of a second dynamic random-access memory;
• obtaining, by the processor, a relationship between the plurality of first indexes of the first dynamic random-access memory and the plurality of second indexes of the second dynamic random-access memory;
• and
• generating, by the processor, a plurality of second coefficients for the second dynamic random-access memory according to the relationship and a plurality of first coefficients of the first dynamic random-access memory;
• wherein the plurality of second coefficients are used to estimate an access latency of the second dynamic random-access memory, and number and the types of the plurality of first indexes are the same as number and types of the plurality of second indexes.